On Tue, Mar 6, 2018 at 9:58 PM, Igor Mammedov wrote:
> On Tue, 6 Mar 2018 11:24:02 +1300
> Michael Clark wrote:
>
> > On Mon, Mar 5, 2018 at 10:44 PM, Igor Mammedov
> wrote:
> >
> > > On Sat, 3 Mar 2018 02:51:31 +1300
> > > Michael Clark wrote:
> > >
> > > > Add CPU state header, CPU definiti
On Tue, 6 Mar 2018 09:58:34 +0100
Igor Mammedov wrote:
> On Tue, 6 Mar 2018 11:24:02 +1300
> Michael Clark wrote:
>
> > On Mon, Mar 5, 2018 at 10:44 PM, Igor Mammedov wrote:
> >
> > > On Sat, 3 Mar 2018 02:51:31 +1300
> > > Michael Clark wrote:
> > >
> > > > Add CPU state header, CPU
On Tue, 6 Mar 2018 11:24:02 +1300
Michael Clark wrote:
> On Mon, Mar 5, 2018 at 10:44 PM, Igor Mammedov wrote:
>
> > On Sat, 3 Mar 2018 02:51:31 +1300
> > Michael Clark wrote:
> >
> > > Add CPU state header, CPU definitions and initialization routines
> > >
> > > Reviewed-by: Richard Hender
On Mon, Mar 5, 2018 at 10:44 PM, Igor Mammedov wrote:
> On Sat, 3 Mar 2018 02:51:31 +1300
> Michael Clark wrote:
>
> > Add CPU state header, CPU definitions and initialization routines
> >
> > Reviewed-by: Richard Henderson
> > Signed-off-by: Sagar Karandikar
> > Signed-off-by: Michael Clark
On Sat, 3 Mar 2018 02:51:31 +1300
Michael Clark wrote:
> Add CPU state header, CPU definitions and initialization routines
>
> Reviewed-by: Richard Henderson
> Signed-off-by: Sagar Karandikar
> Signed-off-by: Michael Clark
> ---
> target/riscv/cpu.c | 432
> +++
Paraphrase this as, we should be closer to reproducing the behaviour of the
SiFive E31, E51, U34 and U54 cores when running RISC-V and SiFive
verification tests. i.e. now if one attempts to configure the MMU on E
cores one will get an illegal instruction trap.
We still have an E21 core to add but
We were able to remove several ifdefs and figured out a problem with
masking out cores for qemu-system-riscv32 and qemu-system-riscv64.
This version of the core patch seems cleaner to me and we have fixed a few
spec compliance issues with regard to alignment of mtvec/stvec when the C
extension is
Add CPU state header, CPU definitions and initialization routines
Reviewed-by: Richard Henderson
Signed-off-by: Sagar Karandikar
Signed-off-by: Michael Clark
---
target/riscv/cpu.c | 432
target/riscv/cpu.h | 296 ++
