Le 16/01/2017 à 20:06, mar.krzeminski a écrit :
W dniu 16.01.2017 o 18:22, Peter Maydell pisze:
On 11 January 2017 at 20:00, Jean-Christophe Dubois
wrote:
The i.MX SPI device was not de-asserting the CS line at the end of
memory access.
This triggered a SIGSEGV in Qemu when the sabrelite emul
W dniu 16.01.2017 o 18:22, Peter Maydell pisze:
On 11 January 2017 at 20:00, Jean-Christophe Dubois
wrote:
The i.MX SPI device was not de-asserting the CS line at the end of
memory access.
This triggered a SIGSEGV in Qemu when the sabrelite emulator was acessing
a SPI flash memory.
Whith thi
On 11 January 2017 at 20:00, Jean-Christophe Dubois
wrote:
> The i.MX SPI device was not de-asserting the CS line at the end of
> memory access.
>
> This triggered a SIGSEGV in Qemu when the sabrelite emulator was acessing
> a SPI flash memory.
>
> Whith this path the CS signal is correctly asser
The i.MX SPI device was not de-asserting the CS line at the end of
memory access.
This triggered a SIGSEGV in Qemu when the sabrelite emulator was acessing
a SPI flash memory.
Whith this path the CS signal is correctly asserted and deasserted arround
memory access.
Assertion level is now based o
