2013/3/1 Peter Maydell :
> On 27 February 2013 07:15, Kuo-Jung Su wrote:
>> From: Kuo-Jung Su
>
> Your subject line could be made a little more specific, like this:
> "hw/nand.c: correct the sense of the BUSY/READY status bit".
>
Got it, thanks
>> The BIT6 of Status Register(SR):
>>
>> SR[6] be
On 27 February 2013 07:15, Kuo-Jung Su wrote:
> From: Kuo-Jung Su
Your subject line could be made a little more specific, like this:
"hw/nand.c: correct the sense of the BUSY/READY status bit".
> The BIT6 of Status Register(SR):
>
> SR[6] behaves the same as R/B# pin
> SR[6] = 0 indicates t
From: Kuo-Jung Su
The BIT6 of Status Register(SR):
SR[6] behaves the same as R/B# pin
SR[6] = 0 indicates the device is busy;
SR[6] = 1 means the device is ready
Some NAND flash controller (i.e. ftnandc021) relies on the SR[6]
to determine if the NAND flash erase/program is success or e
