On 11/04/2015 11:44 PM, Leonid Bloch wrote:
> On Wed, Nov 4, 2015 at 4:46 AM, Jason Wang wrote:
>>
>> On 11/03/2015 07:14 PM, Leonid Bloch wrote:
>>> This implements the following Statistic registers (various counters)
>>> according to Intel's specs:
>>>
>>> TSCTC GOTCL GOTCH GORCL GORCH MP
On Wed, Nov 4, 2015 at 4:46 AM, Jason Wang wrote:
>
>
> On 11/03/2015 07:14 PM, Leonid Bloch wrote:
>> This implements the following Statistic registers (various counters)
>> according to Intel's specs:
>>
>> TSCTC GOTCL GOTCH GORCL GORCH MPRC BPRC RUCROC
>> BPTC MPTC PTC... PRC..
On 11/03/2015 07:14 PM, Leonid Bloch wrote:
> This implements the following Statistic registers (various counters)
> according to Intel's specs:
>
> TSCTC GOTCL GOTCH GORCL GORCH MPRC BPRC RUCROC
> BPTC MPTC PTC... PRC...
>
> Signed-off-by: Leonid Bloch
> Signed-off-by: Dmitry F
This implements the following Statistic registers (various counters)
according to Intel's specs:
TSCTC GOTCL GOTCH GORCL GORCH MPRC BPRC RUCROC
BPTC MPTC PTC... PRC...
Signed-off-by: Leonid Bloch
Signed-off-by: Dmitry Fleytman
---
hw/net/e1000.c | 78 ++
