Re: [Qemu-devel] [PATCH v4 3/9] target-ppc: Implement mtvsrws instruction

2016-09-28 Thread Richard Henderson
On 09/27/2016 10:31 PM, Nikunj A Dadhania wrote: > +tcg_gen_andi_i64(tmp1, cpu_gpr[rA(ctx->opcode)], 0x); > +tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), tmp1, tmp1, 32, 32); > +tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xT(ctx->opcode))); The andi is not necessary;

[Qemu-devel] [PATCH v4 3/9] target-ppc: Implement mtvsrws instruction

2016-09-27 Thread Nikunj A Dadhania
From: Ravi Bangoria mtvsrws: Move To VSR Word & Splat Signed-off-by: Ravi Bangoria Signed-off-by: Nikunj A Dadhania --- target-ppc/translate/vsx-impl.inc.c | 23 +++ target-ppc/translate/vsx-ops.inc.c | 1 + 2 files changed, 24 insertions(+) diff --git a/target-ppc/tran