> From: Janeczek, Craig
> Sent: Tuesday, September 4, 2018 4:44 PM
>
> Subject: RE: [PATCH v4 3/9] target/mips: Split mips instruction handling
>
> To clarify the OPC_MUL here is not an MXU instruction, this is the original
> OPC_MUL that was in the special2 instruction set. The inclusion of this
> From: Janeczek, Craig
> Sent: Tuesday, September 4, 2018 4:44 PM
>
> Subject: RE: [PATCH v4 3/9] target/mips: Split mips instruction handling
>
> To clarify the OPC_MUL here is not an MXU instruction, this is the original
> OPC_MUL that was in the special2 instruction set. The inclusion of this
To clarify the OPC_MUL here is not an MXU instruction, this is the original
OPC_MUL that was in the special2 instruction set. The inclusion of this
instruction in this switch statement is due to the suggested method of
splitting up the mxu commands instruction handling switch statement from the
Hi, Craig,
> From: Craig Janeczek
> Sent: Thursday, August 30, 2018 9:30 PM
> To: qemu-devel@nongnu.org
> Cc: Aleksandar Markovic; aurel...@aurel32.net; Craig Janeczek
> Subject: [PATCH v4 3/9] target/mips: Split mips instruction handling
>
> Splits the instruction handling switch statement from
Splits the instruction handling switch statement from the original
legacy code.
Signed-off-by: Craig Janeczek
---
v1
- NA
v2
- NA
v3
- NA
v4
- Initial patch
target/mips/mips-defs.h | 1 +
target/mips/translate.c | 28 +++-
2 files changed, 28 inserti
