Re: [Qemu-devel] [PATCH v4 2/9] target-ppc: Implement mtvsrdd instruction

2016-09-28 Thread Nikunj A Dadhania
David Gibson writes: > [ Unknown signature status ] > On Wed, Sep 28, 2016 at 11:01:20AM +0530, Nikunj A Dadhania wrote: >> From: Ravi Bangoria >> >> mtvsrdd: Move To VSR Double Doubleword >> >> Signed-off-by: Ravi Bangoria >> Signed-off-by: Nikunj A Dadhania >> --- >> target-ppc/translate/

Re: [Qemu-devel] [PATCH v4 2/9] target-ppc: Implement mtvsrdd instruction

2016-09-28 Thread David Gibson
On Wed, Sep 28, 2016 at 11:01:20AM +0530, Nikunj A Dadhania wrote: > From: Ravi Bangoria > > mtvsrdd: Move To VSR Double Doubleword > > Signed-off-by: Ravi Bangoria > Signed-off-by: Nikunj A Dadhania > --- > target-ppc/translate/vsx-impl.inc.c | 23 +++ > target-ppc/transl

Re: [Qemu-devel] [PATCH v4 2/9] target-ppc: Implement mtvsrdd instruction

2016-09-28 Thread Nikunj A Dadhania
Richard Henderson writes: > On 09/27/2016 10:31 PM, Nikunj A Dadhania wrote: >> +if (!rA(ctx->opcode)) { >> +tcg_gen_movi_i64(cpu_vsrh(xT(ctx->opcode)), 0); >> +} else { >> + tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)]); >> +} > > Indentation. Ot

Re: [Qemu-devel] [PATCH v4 2/9] target-ppc: Implement mtvsrdd instruction

2016-09-28 Thread Richard Henderson
On 09/27/2016 10:31 PM, Nikunj A Dadhania wrote: > +if (!rA(ctx->opcode)) { > +tcg_gen_movi_i64(cpu_vsrh(xT(ctx->opcode)), 0); > +} else { > + tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)]); > +} Indentation. Otherwise, Reviewed-by: Richard Henders

[Qemu-devel] [PATCH v4 2/9] target-ppc: Implement mtvsrdd instruction

2016-09-27 Thread Nikunj A Dadhania
From: Ravi Bangoria mtvsrdd: Move To VSR Double Doubleword Signed-off-by: Ravi Bangoria Signed-off-by: Nikunj A Dadhania --- target-ppc/translate/vsx-impl.inc.c | 23 +++ target-ppc/translate/vsx-ops.inc.c | 1 + 2 files changed, 24 insertions(+) diff --git a/target-ppc