.@redhat.com; Hook, Gary ; qemu-
> de...@nongnu.org
> Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD
> Processor Cache Information
>
> On Wed, Mar 21, 2018 at 08:07:54PM +, Moger, Babu wrote:
> >
> > > -Original Message-
> > >
> Lendacky, Thomas ; Singh, Brijesh
> > ; k...@vger.kernel.org; k...@tripleback.net;
> > mtosa...@redhat.com; Hook, Gary ; qemu-
> > de...@nongnu.org
> > Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD
> > Processor Cache Information
.@redhat.com; Hook, Gary ; qemu-
> de...@nongnu.org
> Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD
> Processor Cache Information
>
> On Wed, Mar 21, 2018 at 05:47:28PM +, Moger, Babu wrote:
> >
> >
> > > -Original Message-
> &
gt; > Lendacky, Thomas ; Singh, Brijesh
> > ; k...@vger.kernel.org; k...@tripleback.net;
> > mtosa...@redhat.com; Hook, Gary ; qemu-
> > de...@nongnu.org
> > Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD
> > Processor Cache Information
> &
tosa...@redhat.com; Hook, Gary ; qemu-
> de...@nongnu.org
> Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD
> Processor Cache Information
>
> On Wed, Mar 21, 2018 at 03:58:41PM +, Moger, Babu wrote:
> > Hi Eduardo,
> >
> > > -Original M
On 2018-03-21 01:09 PM, Eduardo Habkost wrote:
> This makes sense if you want to change a CPU model to enable
> topoext by default. But I suggest setting it for
> ("EPYC" "-" TYPE_X86_CPU) only, not TYPE_X86_CPU, as EPYC is the
> only CPU model affected by patch 4/5.
AIUI, all 17h CPUs have TOPO
at.com;
> > Lendacky, Thomas ; Singh, Brijesh
> > ; k...@vger.kernel.org; k...@tripleback.net;
> > mtosa...@redhat.com; Hook, Gary ; qemu-
> > de...@nongnu.org
> > Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD
> > Processor Cache Informat
> mtosa...@redhat.com; Hook, Gary ; qemu-
> de...@nongnu.org
> Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD
> Processor Cache Information
>
> On Tue, Mar 20, 2018 at 05:25:52PM +, Moger, Babu wrote:
> > Hi Eduardo, Thanks for the comments. Please see
.@redhat.com; Hook, Gary ; qemu-
> de...@nongnu.org
> Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD
> Processor Cache Information
>
> On Tue, Mar 20, 2018 at 05:25:52PM +, Moger, Babu wrote:
> > Hi Eduardo, Thanks for the comments. Please see the res
> > Cc: pbonz...@redhat.com; r...@twiddle.net; rkrc...@redhat.com;
> > Lendacky, Thomas ; Singh, Brijesh
> > ; k...@vger.kernel.org; k...@tripleback.net;
> > mtosa...@redhat.com; Hook, Gary ; qemu-
> > de...@nongnu.org
> > Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386:
ngh, Brijesh
> ; k...@vger.kernel.org; k...@tripleback.net;
> mtosa...@redhat.com; Hook, Gary ; qemu-
> de...@nongnu.org
> Subject: Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD
> Processor Cache Information
>
> On Mon, Mar 12, 2018 at 05:00:46PM -0400, Babu Moger wrote:
On Mon, Mar 12, 2018 at 05:00:46PM -0400, Babu Moger wrote:
> From: Stanislav Lanci
>
> Add information for cpuid 0x801D leaf. Populate cache topology information
> for different cache types(Data Cache, Instruction Cache, L2 and L3) supported
> by 0x801D leaf. Please refer Processor Progr
Hi,
Sorry for not reviewing the previous versions of this series (and
making it miss soft freeze).
On Mon, Mar 12, 2018 at 05:00:46PM -0400, Babu Moger wrote:
> From: Stanislav Lanci
>
> Add information for cpuid 0x801D leaf. Populate cache topology information
> for different cache types(
From: Stanislav Lanci
Add information for cpuid 0x801D leaf. Populate cache topology information
for different cache types(Data Cache, Instruction Cache, L2 and L3) supported
by 0x801D leaf. Please refer Processor Programming Reference (PPR) for AMD
Family 17h Model for more details.
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