On Sun, June 21, 2015 9:37 pm, Paulo Alcantara wrote:
> This interface provides some registers within a 32-byte range and can be
> acessed through PCI-to-LPC bridge interface (PMBASE + 0x60).
>
> It's commonly used as a watchdog timer to detect system lockups through
> SMIs that are generated -- i
On Mon, June 22, 2015 10:07 am, Michael S. Tsirkin wrote:
> On Mon, Jun 22, 2015 at 03:04:13PM +0200, Paolo Bonzini wrote:
>>
>>
>> On 22/06/2015 14:47, Michael S. Tsirkin wrote:
>> > Because it's a pain if I need to move code between files with
>> different
>> > licenses. MIT is GPL compatible b
"Michael S. Tsirkin" writes:
> On Mon, Jun 22, 2015 at 02:32:17PM +0200, Paolo Bonzini wrote:
>>
>>
>> On 22/06/2015 14:30, Paulo Alcantara wrote:
>> >>> >> +/*
>> >>> >> + * QEMU ICH9 TCO emulation
>> >>> >> + *
>> >>> >> + * Copyright (c) 2015 Paulo Alcantara
>> >>> >> + *
>> >>> >> + * Perm
On Mon, Jun 22, 2015 at 03:04:13PM +0200, Paolo Bonzini wrote:
>
>
> On 22/06/2015 14:47, Michael S. Tsirkin wrote:
> > Because it's a pain if I need to move code between files with different
> > licenses. MIT is GPL compatible but mixing licenses at random is still
> > not a good idea.
>
> Thi
On 22/06/2015 14:47, Michael S. Tsirkin wrote:
> Because it's a pain if I need to move code between files with different
> licenses. MIT is GPL compatible but mixing licenses at random is still
> not a good idea.
This is a non-problem. How often does it happen that code is moved
between files
On 22/06/2015 14:44, Michael S. Tsirkin wrote:
> OK. Do you agree to move the ACPI bits to the SSDT, making
> it conditional on device being enabled?
Again, no. The chipset configuration registers range is always defined
by the chipset, even if the TCO is not in use. It would have to be
condit
On Mon, Jun 22, 2015 at 02:32:17PM +0200, Paolo Bonzini wrote:
>
>
> On 22/06/2015 14:30, Paulo Alcantara wrote:
> >>> >> +/*
> >>> >> + * QEMU ICH9 TCO emulation
> >>> >> + *
> >>> >> + * Copyright (c) 2015 Paulo Alcantara
> >>> >> + *
> >>> >> + * Permission is hereby granted, free of charge,
On Mon, Jun 22, 2015 at 09:36:57AM -0300, Paulo Alcantara wrote:
>
> On Mon, June 22, 2015 9:11 am, Michael S. Tsirkin wrote:
> > On Mon, Jun 22, 2015 at 11:45:31AM +0200, Paolo Bonzini wrote:
> >>
> >>
> >> On 22/06/2015 10:43, Michael S. Tsirkin wrote:
> >> > Given that support is known to be pa
On Mon, June 22, 2015 9:11 am, Michael S. Tsirkin wrote:
> On Mon, Jun 22, 2015 at 11:45:31AM +0200, Paolo Bonzini wrote:
>>
>>
>> On 22/06/2015 10:43, Michael S. Tsirkin wrote:
>> > Given that support is known to be partial, would it make sense
>> > to keep it disabled by default for 2.4?
>>
>> W
On 22/06/2015 14:30, Paulo Alcantara wrote:
>>> >> +/*
>>> >> + * QEMU ICH9 TCO emulation
>>> >> + *
>>> >> + * Copyright (c) 2015 Paulo Alcantara
>>> >> + *
>>> >> + * Permission is hereby granted, free of charge, to any person
>>> >> obtaining a copy
>>> >> + * of this software and associated
On Mon, June 22, 2015 5:39 am, Michael S. Tsirkin wrote:
> On Sun, Jun 21, 2015 at 09:37:01PM -0300, Paulo Alcantara wrote:
>> diff --git a/hw/acpi/tco.c b/hw/acpi/tco.c
>> new file mode 100644
>> index 000..b6af1d9
>> --- /dev/null
>> +++ b/hw/acpi/tco.c
>> @@ -0,0 +1,279 @@
>> +/*
>> + * QEM
On Mon, Jun 22, 2015 at 11:45:31AM +0200, Paolo Bonzini wrote:
>
>
> On 22/06/2015 10:43, Michael S. Tsirkin wrote:
> > Given that support is known to be partial, would it make sense
> > to keep it disabled by default for 2.4?
>
> What is partial about it?
Ow, looks like I didn't send out the r
On 22/06/2015 10:43, Michael S. Tsirkin wrote:
> Given that support is known to be partial, would it make sense
> to keep it disabled by default for 2.4?
What is partial about it? In fact, considering that q35 behavior is
still experimental it makes no sense to even make it conditional. We
dis
On Sun, Jun 21, 2015 at 09:37:01PM -0300, Paulo Alcantara wrote:
> This interface provides some registers within a 32-byte range and can be
> acessed through PCI-to-LPC bridge interface (PMBASE + 0x60).
>
> It's commonly used as a watchdog timer to detect system lockups through
> SMIs that are gen
On Sun, Jun 21, 2015 at 09:37:01PM -0300, Paulo Alcantara wrote:
> diff --git a/hw/acpi/tco.c b/hw/acpi/tco.c
> new file mode 100644
> index 000..b6af1d9
> --- /dev/null
> +++ b/hw/acpi/tco.c
> @@ -0,0 +1,279 @@
> +/*
> + * QEMU ICH9 TCO emulation
> + *
> + * Copyright (c) 2015 Paulo Alcantara
This interface provides some registers within a 32-byte range and can be
acessed through PCI-to-LPC bridge interface (PMBASE + 0x60).
It's commonly used as a watchdog timer to detect system lockups through
SMIs that are generated -- if TCO_EN bit is set -- on every timeout. If
NO_REBOOT bit is not
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