On Fri, Aug 16, 2019 at 02:03:23PM -0500, Paul A. Clarke wrote:
65;5603;1c> From: "Paul A. Clarke"
>
> ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR)
> instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl.
> This patch adds support for 'mffsl'.
>
> 'mff
Patchew URL:
https://patchew.org/QEMU/1565982203-11048-1-git-send-email...@us.ibm.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Subject: [Qemu-devel] [PATCH v4] ppc: Add support for 'mffsl' instruction
From: "Paul A. Clarke"
ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR)
instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl.
This patch adds support for 'mffsl'.
'mffsl' is identical to 'mffs', except it only returns mode, status, and enable
bits from th
