Re: [Qemu-devel] [PATCH v4] [i.MX] fix CS handling during SPI access.

2017-01-11 Thread Jean-Christophe DUBOIS
Le 11/01/2017 à 19:08, mar.krzeminski a écrit : W dniu 11.01.2017 o 17:12, Jean-Christophe DUBOIS pisze: Le 10/01/2017 à 00:02, Peter Maydell a écrit : On 9 January 2017 at 22:27, Jean-Christophe DUBOIS wrote: I might be wrong but I think they are coming out of reset with their CS line set to

Re: [Qemu-devel] [PATCH v4] [i.MX] fix CS handling during SPI access.

2017-01-11 Thread mar.krzeminski
W dniu 11.01.2017 o 17:12, Jean-Christophe DUBOIS pisze: Le 10/01/2017 à 00:02, Peter Maydell a écrit : On 9 January 2017 at 22:27, Jean-Christophe DUBOIS wrote: I might be wrong but I think they are coming out of reset with their CS line set to low (so they are selected by default) because th

Re: [Qemu-devel] [PATCH v4] [i.MX] fix CS handling during SPI access.

2017-01-11 Thread Jean-Christophe DUBOIS
Le 10/01/2017 à 00:02, Peter Maydell a écrit : On 9 January 2017 at 22:27, Jean-Christophe DUBOIS wrote: I might be wrong but I think they are coming out of reset with their CS line set to low (so they are selected by default) because this is the default level at reset. If that's true then you

Re: [Qemu-devel] [PATCH v4] [i.MX] fix CS handling during SPI access.

2017-01-09 Thread Peter Maydell
On 9 January 2017 at 22:27, Jean-Christophe DUBOIS wrote: > I might be wrong but I think they are coming out of reset with > their CS line set to low (so they are selected by default) > because this is the default level at reset. If that's true then you're in difficulties, because there's no guar

Re: [Qemu-devel] [PATCH v4] [i.MX] fix CS handling during SPI access.

2017-01-09 Thread Jean-Christophe DUBOIS
Le 09/01/2017 à 22:45, Peter Maydell a écrit : On 9 January 2017 at 21:19, Jean-Christophe DUBOIS wrote: Hum, ... I think I have a problem. With the default register value (that I get a reset) the CS line is deselected when the CS is high. So at reset I would need to set my 4 CS lines to high

Re: [Qemu-devel] [PATCH v4] [i.MX] fix CS handling during SPI access.

2017-01-09 Thread Peter Maydell
On 9 January 2017 at 21:19, Jean-Christophe DUBOIS wrote: > Hum, ... I think I have a problem. > > With the default register value (that I get a reset) the CS line is > deselected when the CS is high. > > So at reset I would need to set my 4 CS lines to high in order to be able to > drive them low

Re: [Qemu-devel] [PATCH v4] [i.MX] fix CS handling during SPI access.

2017-01-09 Thread Jean-Christophe DUBOIS
Hum, ... I think I have a problem. With the default register value (that I get a reset) the CS line is deselected when the CS is high. So at reset I would need to set my 4 CS lines to high in order to be able to drive them low later. So during the "reset" I need to set my 4 CS line to 1 but

Re: [Qemu-devel] [PATCH v4] [i.MX] fix CS handling during SPI access.

2017-01-09 Thread Jean-Christophe DUBOIS
Le 09/01/2017 à 20:06, Peter Maydell a écrit : On 9 January 2017 at 19:04, mar.krzeminski wrote: W dniu 09.01.2017 o 11:46, Peter Maydell pisze: Calling qemu_set_irq() in a device reset function is a bit tricky, because in a full system reset the device at the other end might have already res

Re: [Qemu-devel] [PATCH v4] [i.MX] fix CS handling during SPI access.

2017-01-09 Thread Peter Maydell
On 9 January 2017 at 19:04, mar.krzeminski wrote: > > > W dniu 09.01.2017 o 11:46, Peter Maydell pisze: >> Calling qemu_set_irq() in a device reset function is a bit >> tricky, because in a full system reset the device at the other >> end might have already reset or might not, and calling into >>

Re: [Qemu-devel] [PATCH v4] [i.MX] fix CS handling during SPI access.

2017-01-09 Thread mar.krzeminski
W dniu 09.01.2017 o 11:46, Peter Maydell pisze: On 4 January 2017 at 22:06, Jean-Christophe Dubois wrote: The i.MX SPI device was not de-asserting the CS line at the end of memory access. This triggered a SIGSEGV in Qemu when the sabrelite emulator was acessing a SPI flash memory. Whith thi

Re: [Qemu-devel] [PATCH v4] [i.MX] fix CS handling during SPI access.

2017-01-09 Thread Peter Maydell
On 4 January 2017 at 22:06, Jean-Christophe Dubois wrote: > The i.MX SPI device was not de-asserting the CS line at the end of > memory access. > > This triggered a SIGSEGV in Qemu when the sabrelite emulator was acessing > a SPI flash memory. > > Whith this path the CS signal is correctly asserte

[Qemu-devel] [PATCH v4] [i.MX] fix CS handling during SPI access.

2017-01-04 Thread Jean-Christophe Dubois
The i.MX SPI device was not de-asserting the CS line at the end of memory access. This triggered a SIGSEGV in Qemu when the sabrelite emulator was acessing a SPI flash memory. Whith this path the CS signal is correctly asserted and deasserted arround memory access. Assertion level is now based o