Re: [Qemu-devel] [PATCH v3 08/21] RISC-V TCG Code Generation

2018-01-11 Thread Michael Clark
On Fri, Jan 12, 2018 at 7:15 AM, Michael Clark wrote: > > > On Fri, Jan 12, 2018 at 4:47 AM, Richard Henderson < > richard.hender...@linaro.org> wrote: > >> On 01/10/2018 06:21 PM, Michael Clark wrote: >> > TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU >> > RISC-V code generator

Re: [Qemu-devel] [PATCH v3 08/21] RISC-V TCG Code Generation

2018-01-11 Thread Michael Clark
On Fri, Jan 12, 2018 at 4:47 AM, Richard Henderson < richard.hender...@linaro.org> wrote: > On 01/10/2018 06:21 PM, Michael Clark wrote: > > TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU > > RISC-V code generator has complete coverage for the Base ISA v2.2, > > Privileged ISA v1.

Re: [Qemu-devel] [PATCH v3 08/21] RISC-V TCG Code Generation

2018-01-11 Thread Richard Henderson
On 01/10/2018 06:21 PM, Michael Clark wrote: > TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU > RISC-V code generator has complete coverage for the Base ISA v2.2, > Privileged ISA v1.9.1 and Privileged ISA v1.10: > > - RISC-V Instruction Set Manual Volume I: User-Level ISA Version

[Qemu-devel] [PATCH v3 08/21] RISC-V TCG Code Generation

2018-01-10 Thread Michael Clark
TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU RISC-V code generator has complete coverage for the Base ISA v2.2, Privileged ISA v1.9.1 and Privileged ISA v1.10: - RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2 - RISC-V Instruction Set Manual Volume II: Privile