On Wed, Aug 13, 2014 at 09:48:35AM -0500, Greg Bellows wrote:
> Hi Edgar,
>
> I was just writing a test to verify the correct behavior of the SCR AW/FW
> bits and I think there is an issue.
>
> During an SCR write an initial valid mask is set from SCR_MASK which is
> defined to not include these
Hi Edgar,
I was just writing a test to verify the correct behavior of the SCR AW/FW
bits and I think there is an issue.
During an SCR write an initial valid mask is set from SCR_MASK which is
defined to not include these bits. Then these bits are hard-coded into the
write value using RES1. Last
On Fri, Aug 01, 2014 at 02:34:14PM +0100, Peter Maydell wrote:
> On 17 June 2014 09:45, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias"
> >
> > Signed-off-by: Edgar E. Iglesias
> > ---
> > target-arm/cpu.h| 16 +++-
> > target-arm/helper.c | 31 +++
On 17 June 2014 09:45, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Signed-off-by: Edgar E. Iglesias
> ---
> target-arm/cpu.h| 16 +++-
> target-arm/helper.c | 31 ++-
> 2 files changed, 45 insertions(+), 2 deletions(-)
>
> diff --git a/ta
Reviewed-by: Greg Bellows
On 17 June 2014 03:45, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Signed-off-by: Edgar E. Iglesias
> ---
> target-arm/cpu.h| 16 +++-
> target-arm/helper.c | 31 ++-
> 2 files changed, 45 insertions(+), 2 de
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
target-arm/cpu.h| 16 +++-
target-arm/helper.c | 31 ++-
2 files changed, 45 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index fd57fb5..fa8dee0 100644
-