Re: [Qemu-devel] [PATCH v3 08/12] target-arm: A64: add support for B and BL insns

2013-12-09 Thread Peter Maydell
On 5 December 2013 12:39, Peter Maydell wrote: > From: Alexander Graf > > Implement the B and BL instructions (PC relative branches and calls). > > For convenience in managing TCG temporaries which might be generated > if a source register is the zero-register XZR, we provide a simple > mechanism

Re: [Qemu-devel] [PATCH v3 08/12] target-arm: A64: add support for B and BL insns

2013-12-05 Thread Richard Henderson
On 12/06/2013 01:39 AM, Peter Maydell wrote: > From: Alexander Graf > > Implement the B and BL instructions (PC relative branches and calls). > > For convenience in managing TCG temporaries which might be generated > if a source register is the zero-register XZR, we provide a simple > mechanism

[Qemu-devel] [PATCH v3 08/12] target-arm: A64: add support for B and BL insns

2013-12-05 Thread Peter Maydell
From: Alexander Graf Implement the B and BL instructions (PC relative branches and calls). For convenience in managing TCG temporaries which might be generated if a source register is the zero-register XZR, we provide a simple mechanism for creating a new temp which is automatically freed at the