Thanks.
I wont bother making a change to your patchset for this and will revisit
after things are upstream if a change is needed.
Greg
On 24 June 2014 07:19, Aggeler Fabian wrote:
> Hm…yes, this case is missing, but it is only missing for ARMv7 as this bit
> is RES0 in ARMv8. Even in ARMv7 it
Hm…yes, this case is missing, but it is only missing for ARMv7 as this bit is
RES0 in ARMv8. Even in ARMv7 it is IMPDEF whether
this bit is supported. And since ARMv7 mentions, that this bit is deprecated
from the introduction of Virtualization Extensions
I did not care to add this special case.
On Wed, Jun 11, 2014 at 01:54:47AM +0200, Fabian Aggeler wrote:
> From: Sergey Fedorov
>
> ...from non-secure state.
>
Reviewed-by: Edgar E. Iglesias
> Signed-off-by: Sergey Fedorov
> Signed-off-by: Fabian Aggeler
> ---
> target-arm/helper.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> d
Missing case where it is UNPREDICTABLE to enter FIQ mode from non-secure
state if NSACR.RFR is 1.
On 10 June 2014 18:54, Fabian Aggeler wrote:
> From: Sergey Fedorov
>
> ...from non-secure state.
>
> Signed-off-by: Sergey Fedorov
> Signed-off-by: Fabian Aggeler
> ---
> target-arm/helper.c |
From: Sergey Fedorov
...from non-secure state.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
---
target-arm/helper.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index d8d6637..ace8d8b 100644
--- a/target-arm/helper.c
+++ b/targ
