Re: [Qemu-devel] [PATCH v3] target/ppc: Allow PIR read in privileged mode

On Tue, Jun 05, 2018 at 06:46:12PM +0200, Greg Kurz wrote: > On Mon, 4 Jun 2018 10:53:22 +1000 > David Gibson wrote: > > > On Mon, May 07, 2018 at 01:52:42PM -0300, luporl wrote: > > > According to PowerISA, the PIR register should be readable in privileged > > > mode also, not only in hypervisor

Re: [Qemu-devel] [PATCH v3] target/ppc: Allow PIR read in privileged mode

On Mon, 4 Jun 2018 10:53:22 +1000 David Gibson wrote: > On Mon, May 07, 2018 at 01:52:42PM -0300, luporl wrote: > > According to PowerISA, the PIR register should be readable in privileged > > mode also, not only in hypervisor privileged mode. > > > > PowerISA 3.0 - 4.3.3 Processor Identificatio

Re: [Qemu-devel] [PATCH v3] target/ppc: Allow PIR read in privileged mode

On Mon, May 07, 2018 at 01:52:42PM -0300, luporl wrote: > According to PowerISA, the PIR register should be readable in privileged > mode also, not only in hypervisor privileged mode. > > PowerISA 3.0 - 4.3.3 Processor Identification Register > > "Read access to the PIR is privileged; write acces

[Qemu-devel] [PATCH v3] target/ppc: Allow PIR read in privileged mode

According to PowerISA, the PIR register should be readable in privileged mode also, not only in hypervisor privileged mode. PowerISA 3.0 - 4.3.3 Processor Identification Register "Read access to the PIR is privileged; write access is not provided." Cc: David Gibson Cc: Alexander Graf Cc: qemu-