On Wed, Aug 14, 2019 at 11:34:13AM -0500, Paul Clarke wrote:
> Should these 'checkpatch' ERRORs be addressed, even if it will diverge the
> code style from the existing, surrounding code?
>
> On 8/14/19 11:30 AM, no-re...@patchew.org wrote:
> > This series seems to have some coding style problems
Should these 'checkpatch' ERRORs be addressed, even if it will diverge the code
style from the existing, surrounding code?
On 8/14/19 11:30 AM, no-re...@patchew.org wrote:
> This series seems to have some coding style problems. See output below for
> more information:
> === OUTPUT BEGIN ===
> ER
Patchew URL:
https://patchew.org/QEMU/1565799261-498-1-git-send-email...@us.ibm.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v3] ppc: Add support for 'mffsl' instruction
Message-id: 1565799261
From: "Paul A. Clarke"
ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR)
instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl.
This patch adds support for 'mffsl'.
'mffsl' is identical to 'mffs', except it only returns mode, status, and enable
bits from th
