On 03/21/2018 02:06 AM, Michael Clark wrote:
> Okay, so this would move byte swapping into TCG generic code instead of the
> TCG
> backend, unless the backend explicitly supports load/store with byte swap?
Yes.
r~
On Thu, 22 Mar 2018 15:17:16 PDT (-0700), d...@redhat.com wrote:
"Richard W.M. Jones" writes:
DJ, am I remembering correctly that you tried the test case on the
HiFive evaluation board and it didn't demonstrate the bug?
I tested it on the vc707 board, without seeing the bug.
FWIW, the cores
"Richard W.M. Jones" writes:
> DJ, am I remembering correctly that you tried the test case on the
> HiFive evaluation board and it didn't demonstrate the bug?
I tested it on the vc707 board, without seeing the bug.
I can test other test cases if needed, I've got the board running Fedora
at the m
On Thu, Mar 22, 2018 at 3:17 PM, DJ Delorie wrote:
> "Richard W.M. Jones" writes:
> > DJ, am I remembering correctly that you tried the test case on the
> > HiFive evaluation board and it didn't demonstrate the bug?
>
> I tested it on the vc707 board, without seeing the bug.
>
> I can test other
On Thu, Mar 22, 2018 at 02:06:24PM -0700, Michael Clark wrote:
> On Mon, Mar 19, 2018 at 2:39 PM, Michael Clark wrote:
> > On Mon, Mar 19, 2018 at 12:42 PM, Richard W.M. Jones
> > wrote:
> >> Did you see the problem with restoring floating point registers on
> >> context switch? The test case is
On Mon, Mar 19, 2018 at 2:39 PM, Michael Clark wrote:
>
>
> On Mon, Mar 19, 2018 at 12:42 PM, Richard W.M. Jones
> wrote:
>
>> On Mon, Mar 19, 2018 at 11:35:51AM -0700, Michael Clark wrote:
>> > The RISC-V post-merge spec conformance and cleanup series has had a lot
>> of
>> > testing. I've been
On Mon, Mar 19, 2018 at 9:43 PM, Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 03/20/2018 02:35 AM, Michael Clark wrote:
> > FYI - I also have an experimental branch containing a RISC-V TCG back-end
> > that I started on during the RISC-V Hackathon in Portland last week:
> >
> > -
On 03/20/2018 02:35 AM, Michael Clark wrote:
> FYI - I also have an experimental branch containing a RISC-V TCG back-end
> that I started on during the RISC-V Hackathon in Portland last week:
>
> - https://github.com/michaeljclark/riscv-qemu/tree/wip-riscv-tcg-backend
Cool.
> I'm able to run a v
On Mon, Mar 19, 2018 at 12:42 PM, Richard W.M. Jones
wrote:
> On Mon, Mar 19, 2018 at 11:35:51AM -0700, Michael Clark wrote:
> > The RISC-V post-merge spec conformance and cleanup series has had a lot
> of
> > testing. I've been using it to compile QEMU inside of QEMU using the
> RISC-V
> > Fedor
On Mon, Mar 19, 2018 at 11:35:51AM -0700, Michael Clark wrote:
> The RISC-V post-merge spec conformance and cleanup series has had a lot of
> testing. I've been using it to compile QEMU inside of QEMU using the RISC-V
> Fedora Image and its native RISC-V GCC toolchain running inside SMP Linux
> 4.1
On Sun, Mar 18, 2018 at 4:22 PM, Philippe Mathieu-Daudé
wrote:
> On 03/16/2018 06:26 PM, Michael Clark wrote:
> > This version uses a constant size memory buffer sized for
> > the maximum possible ISA string length. It also uses g_new
> > instead of g_new0, uses more efficient logic to append
> >
On 03/16/2018 06:26 PM, Michael Clark wrote:
> This version uses a constant size memory buffer sized for
> the maximum possible ISA string length. It also uses g_new
> instead of g_new0, uses more efficient logic to append
> extensions and adds manual zero termination of the string.
>
> Cc: Palmer
This version uses a constant size memory buffer sized for
the maximum possible ISA string length. It also uses g_new
instead of g_new0, uses more efficient logic to append
extensions and adds manual zero termination of the string.
Cc: Palmer Dabbelt
Cc: Peter Maydell
Cc: Philippe Mathieu-Daudé
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