W dniu 06.01.2017 o 19:18, Jean-Christophe DUBOIS pisze:
Le 06/01/2017 à 13:28, mar.krzeminski a écrit :
Please make sure that in HW ECSPI_CONFIGREG_SS_POL bits are 0's
after reset/power up (defaults).
There is already a memset to 0 of all regs (including CONFIGREG) in
the reset function.
I
Le 06/01/2017 à 13:28, mar.krzeminski a écrit :
Please make sure that in HW ECSPI_CONFIGREG_SS_POL bits are 0's
after reset/power up (defaults).
There is already a memset to 0 of all regs (including CONFIGREG) in
the reset function.
I saw that memset, my question is rather real HW also have 0s
W dniu 04.01.2017 o 22:54, Jean-Christophe DUBOIS pisze:
Le 04/01/2017 à 21:56, mar.krzeminski a écrit :
W dniu 03.01.2017 o 21:35, Jean-Christophe Dubois pisze:
The i.MX SPI device was not de-asserting the CS line at the end of
memory access.
This triggered a SIGSEGV in Qemu when the sabr
Le 04/01/2017 à 21:56, mar.krzeminski a écrit :
W dniu 03.01.2017 o 21:35, Jean-Christophe Dubois pisze:
The i.MX SPI device was not de-asserting the CS line at the end of
memory access.
This triggered a SIGSEGV in Qemu when the sabrelite emulator was
acessing
a SPI flash memory.
Whit this
W dniu 03.01.2017 o 21:35, Jean-Christophe Dubois pisze:
The i.MX SPI device was not de-asserting the CS line at the end of
memory access.
This triggered a SIGSEGV in Qemu when the sabrelite emulator was acessing
a SPI flash memory.
Whit this path the CS signal is correctly asserted and deass
The i.MX SPI device was not de-asserting the CS line at the end of
memory access.
This triggered a SIGSEGV in Qemu when the sabrelite emulator was acessing
a SPI flash memory.
Whit this path the CS signal is correctly asserted and deasserted arround
memory access.
Assertion level is now based on
