Re: [Qemu-devel] [PATCH v2 5/6] target-mips: Support for Cavium specific instructions

2011-10-21 Thread Richard Henderson
On 10/21/2011 01:17 AM, kha...@kics.edu.pk wrote: > +switch (opc) { > +case OPC_SEQ: > +tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr[rd], t0, 1); > +opn = "seq"; > +break; > +case OPC_SNE: > +tcg_gen_setcondi_tl(TCG_COND_GTU, cpu_gpr[rd], t0, 0); > +

[Qemu-devel] [PATCH v2 5/6] target-mips: Support for Cavium specific instructions

2011-10-21 Thread khansa
From: Khansa Butt Signed-off-by: Khansa Butt Signed-off-by: Ehsan Ul Haq Signed-off-by: Abdul Qadeer Signed-off-by: Abdul Waheed --- target-mips/cpu.h |7 + target-mips/helper.h|5 + target-mips/machine.c | 12 ++ target-mips/op_helper.c | 73 target-mips/tr