On 2018-06-30 08:05, Paolo Bonzini wrote:
> On 30/06/2018 07:25, Jan Kiszka wrote:
>> On 2018-06-27 14:14, Paolo Bonzini wrote:
>>> On 03/04/2018 17:36, Jan Kiszka wrote:
+static hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType
access_type,
+
On 30/06/2018 07:25, Jan Kiszka wrote:
> On 2018-06-27 14:14, Paolo Bonzini wrote:
>> On 03/04/2018 17:36, Jan Kiszka wrote:
>>>
>>> +static hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType
>>> access_type,
>>> +int *prot)
>>> +{
>>> +CPUX86State *env = &X86
On 2018-06-27 14:14, Paolo Bonzini wrote:
> On 03/04/2018 17:36, Jan Kiszka wrote:
>>
>> +static hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType
>> access_type,
>> +int *prot)
>> +{
>> +CPUX86State *env = &X86_CPU(cs)->env;
>> +uint64_t rsvd_mask = PG_H
On 03/04/2018 17:36, Jan Kiszka wrote:
>
> +static hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType
> access_type,
> +int *prot)
> +{
> +CPUX86State *env = &X86_CPU(cs)->env;
> +uint64_t rsvd_mask = PG_HI_RSVD_MASK;
> +uint64_t ptep, pte;
> +uint
From: Jan Kiszka
This implements NPT suport for SVM by hooking into
x86_cpu_handle_mmu_fault where it reads the stage-1 page table. Whether
we need to perform this 2nd stage translation, and how, is decided
during vmrun and stored in hflags as well as nested_cr3 and
nested_pg_mode.
As get_hphys
