On 05/25/2017 01:50 PM, Aurelien Jarno wrote:
On 2017-05-24 12:22, Richard Henderson wrote:
(1) The OR of the low bits or R1 into INSN were not being done
consistently; it was forgotten along all but the SVC path.
It was done for the logical ops assuming the instruction has the
corresponding b
On 2017-05-24 12:22, Richard Henderson wrote:
> (1) The OR of the low bits or R1 into INSN were not being done
> consistently; it was forgotten along all but the SVC path.
It was done for the logical ops assuming the instruction has the
corresponding byte set to 0, as in that case it matches the l
(1) The OR of the low bits or R1 into INSN were not being done
consistently; it was forgotten along all but the SVC path.
(2) The setting of ILEN was wrong on SVC path for EXRL.
(3) The data load for ICM read too much.
Fix these by consolidating data load at the beginning, using
get_ilen to contro
