Re: [Qemu-devel] [PATCH v2 3/7] memory: iommu support

2012-11-01 Thread Avi Kivity
On 11/01/2012 03:44 PM, Avi Kivity wrote: > > However we do have a problem with non-1/2/4/8 byte writes. Right now > any mismatched access ends up as an 8 byte write, we need an extra > accessor for arbitrary writes, or rather better use of the .impl members > of MemoryRegionOps. Sorry, it's con

Re: [Qemu-devel] [PATCH v2 3/7] memory: iommu support

2012-11-01 Thread Avi Kivity
On 10/31/2012 08:59 PM, Benjamin Herrenschmidt wrote: > On Wed, 2012-10-31 at 12:32 +0200, Avi Kivity wrote: >> This has nothing to do with device endianness; we're translating from a >> byte buffer (address_space_rw()) to a uint64_t >> (MemoryRegionOps::read/write()) so we need to take host endian

Re: [Qemu-devel] [PATCH v2 3/7] memory: iommu support

2012-10-31 Thread Benjamin Herrenschmidt
On Wed, 2012-10-31 at 12:32 +0200, Avi Kivity wrote: > This has nothing to do with device endianness; we're translating from a > byte buffer (address_space_rw()) to a uint64_t > (MemoryRegionOps::read/write()) so we need to take host endianess into > account. > > This code cleverly makes use of me

Re: [Qemu-devel] [PATCH v2 3/7] memory: iommu support

2012-10-31 Thread Avi Kivity
On 10/30/2012 09:11 PM, Blue Swirl wrote: > On Tue, Oct 30, 2012 at 11:47 AM, Avi Kivity wrote: >> Add a new memory region type that translates addresses it is given, >> then forwards them to a target address space. This is similar to >> an alias, except that the mapping is more flexible than a l

Re: [Qemu-devel] [PATCH v2 3/7] memory: iommu support

2012-10-30 Thread Blue Swirl
On Tue, Oct 30, 2012 at 8:03 PM, Benjamin Herrenschmidt wrote: > On Tue, 2012-10-30 at 19:11 +, Blue Swirl wrote: > >> Why couple this with host endianness? I'd expect IOMMU to operate at >> target bus endianness, for example LE for PCI on PPC guest. > > I'm not sure about putting the iommu "i

Re: [Qemu-devel] [PATCH v2 3/7] memory: iommu support

2012-10-30 Thread Benjamin Herrenschmidt
On Tue, 2012-10-30 at 19:11 +, Blue Swirl wrote: > Why couple this with host endianness? I'd expect IOMMU to operate at > target bus endianness, for example LE for PCI on PPC guest. I'm not sure about putting the iommu "in charge" of endianness ... On one hand it's fishy. It should be 'trans

Re: [Qemu-devel] [PATCH v2 3/7] memory: iommu support

2012-10-30 Thread Blue Swirl
On Tue, Oct 30, 2012 at 11:47 AM, Avi Kivity wrote: > Add a new memory region type that translates addresses it is given, > then forwards them to a target address space. This is similar to > an alias, except that the mapping is more flexible than a linear > translation and trucation, and also les

[Qemu-devel] [PATCH v2 3/7] memory: iommu support

2012-10-30 Thread Avi Kivity
Add a new memory region type that translates addresses it is given, then forwards them to a target address space. This is similar to an alias, except that the mapping is more flexible than a linear translation and trucation, and also less efficient since the translation happens at runtime. The im