Re: [Qemu-devel] [PATCH v2 15/17] RISC-V: add vector extension reduction instructions

On 9/11/19 2:25 AM, liuzhiwei wrote: > +/* vredsum.vs vd, vs2, vs1, vm # vd[0] = sum(vs1[0] , vs2[*]) */ > +void VECTOR_HELPER(vredsum_vs)(CPURISCVState *env, uint32_t vm, uint32_t rs1, > +uint32_t rs2, uint32_t rd) > +{ > > +int width, lmul, vl, vlmax; > +int i, j, src2; > +uint6

[Qemu-devel] [PATCH v2 15/17] RISC-V: add vector extension reduction instructions

From: LIU Zhiwei Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 17 + target/riscv/insn32.decode | 17 + target/riscv/insn_trans/trans_rvv.inc.c | 17 + target/riscv/vector_helper.c| 1275 +++ 4 files changed, 1