Re: [Qemu-devel] [PATCH v2 13/22] target/openrisc: Fix cpu_mmu_index

2018-06-28 Thread Stafford Horne
On Wed, Jun 27, 2018 at 06:36:20PM -0700, Richard Henderson wrote: > On 06/27/2018 04:08 PM, Stafford Horne wrote: > > I am still getting failures on SMP, this time the kernel is jumping to some > > unknown address, maybe an itlb issue, I will continue to debug. Bisecting > > it is > > exposing s

Re: [Qemu-devel] [PATCH v2 13/22] target/openrisc: Fix cpu_mmu_index

2018-06-27 Thread Richard Henderson
On 06/27/2018 04:08 PM, Stafford Horne wrote: > I am still getting failures on SMP, this time the kernel is jumping to some > unknown address, maybe an itlb issue, I will continue to debug. Bisecting it > is > exposing some other issues (the mmu handlers were not getting init'd during > one > po

Re: [Qemu-devel] [PATCH v2 13/22] target/openrisc: Fix cpu_mmu_index

2018-06-27 Thread Stafford Horne
On Wed, Jun 27, 2018 at 06:50:18AM -0700, Richard Henderson wrote: > On 06/27/2018 05:59 AM, Stafford Horne wrote: > > The index is negative... this patch should fix that. > > > > @@ -78,6 +78,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong > > spr, > > target_ulong rb) > > case

Re: [Qemu-devel] [PATCH v2 13/22] target/openrisc: Fix cpu_mmu_index

2018-06-27 Thread Richard Henderson
On 06/27/2018 05:59 AM, Stafford Horne wrote: > The index is negative... this patch should fix that. > > @@ -78,6 +78,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, > target_ulong rb) > case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */ > idx =

Re: [Qemu-devel] [PATCH v2 13/22] target/openrisc: Fix cpu_mmu_index

2018-06-27 Thread Stafford Horne
On Tue, Jun 26, 2018 at 03:26:01PM -0700, Richard Henderson wrote: > On 06/26/2018 03:07 PM, Stafford Horne wrote: > > Hello, > > > > I think I found out something. > > > > in: target/openrisc/sys_helper.c:92 > > > > When we write to `env->tlb.dtlb[idx].tr` in helper_mtspr(): > > 93

Re: [Qemu-devel] [PATCH v2 13/22] target/openrisc: Fix cpu_mmu_index

2018-06-26 Thread Richard Henderson
On 06/26/2018 03:07 PM, Stafford Horne wrote: > Hello, > > I think I found out something. > > in: target/openrisc/sys_helper.c:92 > > When we write to `env->tlb.dtlb[idx].tr` in helper_mtspr(): > 93 case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): > /* DTLBW0TR 0-127 */ > 94

Re: [Qemu-devel] [PATCH v2 13/22] target/openrisc: Fix cpu_mmu_index

2018-06-26 Thread Stafford Horne
Hello, I think I found out something. in: target/openrisc/sys_helper.c:92 When we write to `env->tlb.dtlb[idx].tr` in helper_mtspr(): 93 case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */ 94 idx = spr - TO_SPR(1, 640); 95 env->tl

Re: [Qemu-devel] [PATCH v2 13/22] target/openrisc: Fix cpu_mmu_index

2018-06-23 Thread Stafford Horne
On Tue, Jun 19, 2018 at 3:41 AM Richard Henderson wrote: > > The code in cpu_mmu_index does not properly honor SR_DME. > This bug has workarounds elsewhere in that we flush the > tlb more often than necessary, on the state changes that > should be reflected in a change of mmu_index. > > Fixing thi

[Qemu-devel] [PATCH v2 13/22] target/openrisc: Fix cpu_mmu_index

2018-06-18 Thread Richard Henderson
The code in cpu_mmu_index does not properly honor SR_DME. This bug has workarounds elsewhere in that we flush the tlb more often than necessary, on the state changes that should be reflected in a change of mmu_index. Fixing this means that we can respect the mmu_index that is given to tlb_flush.