Re: [Qemu-devel] [PATCH v2 1/9] target-mips: add KScratch registers

2014-10-20 Thread Leon Alrae
Hi Yongbok, On 14/10/2014 14:59, Yongbok Kim wrote: >> @@ -4611,6 +4612,15 @@ static inline void gen_mtc0_store64 (TCGv arg, >> target_ulong off) >> tcg_gen_st_tl(arg, cpu_env, off); >> } >> +static inline void gen_mfc0_unimplemented(DisasContext *ctx, TCGv arg) >> +{ >> +if (ctx->in

Re: [Qemu-devel] [PATCH v2 1/9] target-mips: add KScratch registers

2014-10-14 Thread Yongbok Kim
Not related code changes are included. See the comment below. Other than, Reviewed-by: Yongbok Kim Regards, Yongbok On 08/07/2014 08:57, Leon Alrae wrote: KScratch Registers (CP0 Register 31, Selects 2 to 7) The KScratch registers are read/write registers available for scratch pad storage b

[Qemu-devel] [PATCH v2 1/9] target-mips: add KScratch registers

2014-07-08 Thread Leon Alrae
KScratch Registers (CP0 Register 31, Selects 2 to 7) The KScratch registers are read/write registers available for scratch pad storage by kernel mode software. They are 32-bits in width for 32-bit processors and 64-bits for 64-bit processors. CP0Config4.KScrExist[2:7] bits indicate presence of CP