On 01/17/2017 06:34 PM, mar.krzeminski wrote:
+static void test_write_page_mem(void)
+{
+uint32_t my_page_addr = 0x15000 * PAGE_SIZE;
+uint32_t page[PAGE_SIZE / 4];
+int i;
+
+/* Enable 4BYTE mode for controller. This is should be strapped by
W dniu 17.01.2017 o 09:34, Cédric Le Goater pisze:
On 01/16/2017 06:51 PM, mar.krzeminski wrote:
W dniu 09.01.2017 o 17:24, Cédric Le Goater pisze:
The Aspeed SMC controllers have a mode (Command mode) in which
accesses to the flash content are no different than doing MMIOs. The
controller g
On 01/16/2017 06:51 PM, mar.krzeminski wrote:
>
>
> W dniu 09.01.2017 o 17:24, Cédric Le Goater pisze:
>> The Aspeed SMC controllers have a mode (Command mode) in which
>> accesses to the flash content are no different than doing MMIOs. The
>> controller generates all the necessary commands to lo
W dniu 09.01.2017 o 17:24, Cédric Le Goater pisze:
The Aspeed SMC controllers have a mode (Command mode) in which
accesses to the flash content are no different than doing MMIOs. The
controller generates all the necessary commands to load (or store)
data in memory.
So add a couple of tests doi
The Aspeed SMC controllers have a mode (Command mode) in which
accesses to the flash content are no different than doing MMIOs. The
controller generates all the necessary commands to load (or store)
data in memory.
So add a couple of tests doing direct reads and writes on the AHB bus.
Signed-off-
