On 12/6/18 7:49 AM, Peter Maydell wrote:
>> +uint64_t hcr = arm_hcr_el2_eff(env);
>> +if (hcr & HCR_E2H) {
>> +hcr &= HCR_TLOR;
>> +} else {
>> +hcr &= HCR_TGE | HCR_TLOR;
> This doesn't make sense to me
The logic is backward. What I was after was
On Mon, 3 Dec 2018 at 20:38, Richard Henderson
wrote:
>
> Provide a trivial implementation with zero limited ordering regions,
> which causes the LDLAR and STLLR instructions to devolve into the
> LDAR and STLR instructions from the base ARMv8.0 instruction set.
>
> Signed-off-by: Richard Henderso
On 12/6/18 7:49 AM, Peter Maydell wrote:
>> +static inline bool isar_feature_aa64_lor(const ARMISARegisters *id)
>> +{
>> +return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR1, LO) != 0;
>
> You're testing the wrong ID register here...
Oops, I thought I fixed that...
>> +static CPAccessResult ac
Provide a trivial implementation with zero limited ordering regions,
which causes the LDLAR and STLLR instructions to devolve into the
LDAR and STLR instructions from the base ARMv8.0 instruction set.
Signed-off-by: Richard Henderson
---
v2: Mark LORID_EL1 read-only.
Add TLOR access checks.
