On Fri, 12 Jan 2018 00:09:16 PST (-0800), h...@lst.de wrote:
On Fri, Jan 12, 2018 at 07:24:54AM +1300, Michael Clark wrote:
I'm going to be restoring branches for bbl and riscv-linux that work again
priv 1.9.1. There are still other emulators and RTL that support priv1.9.1.
Folk will have silico
On Fri, Jan 12, 2018 at 07:24:54AM +1300, Michael Clark wrote:
> I'm going to be restoring branches for bbl and riscv-linux that work again
> priv 1.9.1. There are still other emulators and RTL that support priv1.9.1.
> Folk will have silicon against different versions of spec going forward.
> Like
On Wed, 10 Jan 2018 23:58:12 PST (-0800), h...@lst.de wrote:
On Wed, Jan 10, 2018 at 03:46:19PM -0800, Michael Clark wrote:
- RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2
- RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1
- RISC-V Instruction Set Manual
We've been asked to address the spec versioning problem in QEMU.
I'm going to be restoring branches for bbl and riscv-linux that work again
priv 1.9.1. There are still other emulators and RTL that support priv1.9.1.
Folk will have silicon against different versions of spec going forward.
Likewise
On Wed, Jan 10, 2018 at 03:46:19PM -0800, Michael Clark wrote:
> - RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2
> - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1
> - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10
Same question as
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1515628000-93285-1-git-send-email-...@sifive.com
Subject: [Qemu-devel] [PATCH v2 00/21] RISC-V QEMU Port Submission v2
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
FYI - I intended these emails to go to the RISC-V Patches but unfortunately
had the wrong address on the 'cc.
This time around, the patches are in the qemu-devel archives here:
- http://lists.nongnu.org/archive/html/qemu-devel/2018-01/threads.html
On Thu, Jan 11, 2018 at 12:46 PM, Michael Clark
QEMU RISC-V Emulation Support (RV64GC, RV32GC)
This patch series has major clean ups to target/riscv. There may be
some feedback that has been missed however the changelog is growing
quite large so we have decided to respin the patch series. No new
features have been added however a number of bugs
