On 15 May 2015 at 22:01, Peter Crosthwaite wrote:
> I'm guessing I need a signed key for that. Anyone know of someone in
> San Francisco bay-area able to sign me?
At the moment we're requiring signed tags, but not necessarily
that all submaintainers have a web-of-trust path from me to
them (thoug
On Fri, May 15, 2015 at 6:33 AM, Richard Henderson wrote:
> On 05/14/2015 09:52 PM, Peter Crosthwaite wrote:
>> Ping!
>>
>> Richard has RB'd the core stuff but do we need CPU arch maintainer
>> acks on the latter patches?
>
> Yes, I'd prefer especially the arm patches get another look.
>
>> What q
On Fri, May 15, 2015 at 6:33 AM, Richard Henderson wrote:
> On 05/14/2015 09:52 PM, Peter Crosthwaite wrote:
>> Ping!
>>
>> Richard has RB'd the core stuff but do we need CPU arch maintainer
>> acks on the latter patches?
>
> Yes, I'd prefer especially the arm patches get another look.
>
>> What q
On 05/14/2015 09:52 PM, Peter Crosthwaite wrote:
> Ping!
>
> Richard has RB'd the core stuff but do we need CPU arch maintainer
> acks on the latter patches?
Yes, I'd prefer especially the arm patches get another look.
> What queue should this go via? TCG?
QOM via Andreas would be my first pref
Ping!
Richard has RB'd the core stuff but do we need CPU arch maintainer
acks on the latter patches?
What queue should this go via? TCG?
Regards,
Peter
On Sat, May 9, 2015 at 1:11 PM, Peter Crosthwaite
wrote:
> These two functions are mostly trying to do the same thing, which is
> disassemble
These two functions are mostly trying to do the same thing, which is
disassemble a target instruction (sequence) for printfing. The
architecture specific setup is largely duped between the two functions.
The approach is to add a single QOM hook on the CPU level to setup the
disassembler (P1&2). Th
