On 1 September 2014 15:50, Peter Maydell wrote:
> On 1 September 2014 12:55, Ard Biesheuvel wrote:
>> Currently, booting multiple cores under TCG is unstable, so the restriction
>> to 1 cpu in TCG mode is retained for now. However, PSCI reset and poweroff
>> are
>> supported.
>
> This is worryin
On 1 September 2014 12:55, Ard Biesheuvel wrote:
> Currently, booting multiple cores under TCG is unstable, so the restriction
> to 1 cpu in TCG mode is retained for now. However, PSCI reset and poweroff are
> supported.
This is worrying, incidentally. What's the instability? Last time I
tried Ro
This series adds PSCI support to ARM and AArch64 system emulation when running
in TCG mode. As PSCI calls can be made using either hypervisor call (HVC) or
secure monitor call (SMC) instructions, support is added for handling those
in patch #3 before patch #4 adds the actual PSCI dispatch logic. Pa
