Re: [Qemu-devel] [PATCH v2] target-mips: simplify LWL/LDL mask generation

2015-07-23 Thread Richard Henderson
On 07/15/2015 08:05 AM, Aurelien Jarno wrote: > The LWL/LDL instructions mask the GPR with a mask depending on the > address alignement. It is currently computed by doing: > > mask = 0x7fffull >> (t1 ^ 63) > > It's simpler to generate it by doing: > > mask = ~(-1 << t1) > >

[Qemu-devel] [PATCH v2] target-mips: simplify LWL/LDL mask generation

2015-07-15 Thread Aurelien Jarno
The LWL/LDL instructions mask the GPR with a mask depending on the address alignement. It is currently computed by doing: mask = 0x7fffull >> (t1 ^ 63) It's simpler to generate it by doing: mask = ~(-1 << t1) It uses one TCG instruction less, and it avoids a 32/64-bit consta