Re: [Qemu-devel] [PATCH v1 3/5] RISC-V: Update CSR and interrupt definitions

2018-10-10 Thread Palmer Dabbelt
On Mon, 08 Oct 2018 11:25:36 PDT (-0700), alistair.fran...@wdc.com wrote: From: Michael Clark * Add user-mode CSR defininitions. * Reorder CSR definitions to match the specification. * Change H mode interrupt comment to 'reserved'. * Remove unused X_COP interrupt. * Add user-mode interrupts. *

[Qemu-devel] [PATCH v1 3/5] RISC-V: Update CSR and interrupt definitions

2018-10-08 Thread Alistair Francis
From: Michael Clark * Add user-mode CSR defininitions. * Reorder CSR definitions to match the specification. * Change H mode interrupt comment to 'reserved'. * Remove unused X_COP interrupt. * Add user-mode interrupts. * Remove erroneous until comments on machine mode interrupts. * Move together