Re: [Qemu-devel] [PATCH v1 18/21] SiFive RISC-V PRCI Block

2018-01-03 Thread Michael Clark
On Thu, Jan 4, 2018 at 4:02 AM, KONRAD Frederic wrote: > > > On 01/03/2018 01:44 AM, Michael Clark wrote: > >> Simple model of the PRCI (Power, Reset, Clock, Interrupt) to emulate >> register reads made by the SDK BSP. >> >> Signed-off-by: Michael Clark >> --- >> hw/riscv/sifive_prci.c

Re: [Qemu-devel] [PATCH v1 18/21] SiFive RISC-V PRCI Block

2018-01-03 Thread KONRAD Frederic
On 01/03/2018 01:44 AM, Michael Clark wrote: Simple model of the PRCI (Power, Reset, Clock, Interrupt) to emulate register reads made by the SDK BSP. Signed-off-by: Michael Clark --- hw/riscv/sifive_prci.c | 107 + include/hw/riscv/sifive_pr

[Qemu-devel] [PATCH v1 18/21] SiFive RISC-V PRCI Block

2018-01-02 Thread Michael Clark
Simple model of the PRCI (Power, Reset, Clock, Interrupt) to emulate register reads made by the SDK BSP. Signed-off-by: Michael Clark --- hw/riscv/sifive_prci.c | 107 + include/hw/riscv/sifive_prci.h | 43 + 2 files changed, 150