Re: [Qemu-devel] [PATCH v1 15/21] RISC-V Spike Machines

2018-01-03 Thread Richard Henderson
On 01/02/2018 04:44 PM, Michael Clark wrote: > +object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", > +&error_abort); Ah, right. Nevermind my previous question. r~

[Qemu-devel] [PATCH v1 15/21] RISC-V Spike Machines

2018-01-02 Thread Michael Clark
RISC-V machines compatble with Spike aka riscv-isa-sim, the RISC-V Instruction Set Simulator. The following machines are implemented: - 'spike_v1.9'; HTIF console, config-string, Privileged ISA Version 1.9.1 - 'spike_v1.10'; HTIF console, device-tree, Privileged ISA Version 1.10 Signed-off-by: Mi