On 01/05/2018 03:41 PM, Antony Pavlov wrote:
> On Wed, 3 Jan 2018 13:44:16 +1300
> Michael Clark wrote:
>
>> Holds the state of a heterogenous array of RISC-V hardware threads.
>
>
> Hmm, you use SysBusDevice, uint32_t and RISCVCPU types but there is no header
> files
> inclusion to define t
On Wed, 3 Jan 2018 13:44:16 +1300
Michael Clark wrote:
> Holds the state of a heterogenous array of RISC-V hardware threads.
...
> --- /dev/null
> +++ b/include/hw/riscv/riscv_hart.h
> @@ -0,0 +1,45 @@
> +/*
> + * QEMU RISC-V Hart Array interface
> + *
> + * Copyright (c) 2017 SiFive, Inc.
> +
On 01/02/2018 04:44 PM, Michael Clark wrote:
> Holds the state of a heterogenous array of RISC-V hardware threads.
At the moment they are homogeneous, since they are all created from the same
cpu_model. Is that the ultimate intent?
> +static Property riscv_harts_props[] = {
> +DEFINE_PROP_UI
Holds the state of a heterogenous array of RISC-V hardware threads.
Signed-off-by: Michael Clark
---
hw/riscv/riscv_hart.c | 95 +++
include/hw/riscv/riscv_hart.h | 45
2 files changed, 140 insertions(+)
create mode 100644 hw/
