Re: [Qemu-devel] [PATCH v1 1/1] cadence_gem: Correct Marvell PHY SPCFC reset value

2015-09-08 Thread Peter Maydell
On 3 September 2015 at 23:10, Alistair Francis wrote: > Bit 15 of the PHY Specific Status Register is reserved and > should remain 0. Fix the reset value to ensure that the 15th > bit is not set. > > Signed-off-by: Alistair Francis > --- > http://www.marvell.com/transceivers/assets/Marvell-88E301

Re: [Qemu-devel] [PATCH v1 1/1] cadence_gem: Correct Marvell PHY SPCFC reset value

2015-09-04 Thread Edgar E. Iglesias
On Fri, Sep 04, 2015 at 07:12:23PM +0100, Peter Maydell wrote: > On 4 September 2015 at 19:00, Alistair Francis > wrote: > > On Thu, Sep 3, 2015 at 3:56 PM, Edgar E. Iglesias > > wrote: > >> On Thu, Sep 03, 2015 at 03:10:52PM -0700, Alistair Francis wrote: > >>> Bit 15 of the PHY Specific Status

Re: [Qemu-devel] [PATCH v1 1/1] cadence_gem: Correct Marvell PHY SPCFC reset value

2015-09-04 Thread Alistair Francis
On Fri, Sep 4, 2015 at 11:12 AM, Peter Maydell wrote: > On 4 September 2015 at 19:00, Alistair Francis > wrote: >> On Thu, Sep 3, 2015 at 3:56 PM, Edgar E. Iglesias >> wrote: >>> On Thu, Sep 03, 2015 at 03:10:52PM -0700, Alistair Francis wrote: Bit 15 of the PHY Specific Status Register is

Re: [Qemu-devel] [PATCH v1 1/1] cadence_gem: Correct Marvell PHY SPCFC reset value

2015-09-04 Thread Peter Maydell
On 4 September 2015 at 19:00, Alistair Francis wrote: > On Thu, Sep 3, 2015 at 3:56 PM, Edgar E. Iglesias > wrote: >> On Thu, Sep 03, 2015 at 03:10:52PM -0700, Alistair Francis wrote: >>> Bit 15 of the PHY Specific Status Register is reserved and >>> should remain 0. Fix the reset value to ensure

Re: [Qemu-devel] [PATCH v1 1/1] cadence_gem: Correct Marvell PHY SPCFC reset value

2015-09-04 Thread Alistair Francis
On Thu, Sep 3, 2015 at 3:56 PM, Edgar E. Iglesias wrote: > On Thu, Sep 03, 2015 at 03:10:52PM -0700, Alistair Francis wrote: >> Bit 15 of the PHY Specific Status Register is reserved and >> should remain 0. Fix the reset value to ensure that the 15th >> bit is not set. >> >> Signed-off-by: Alistai

Re: [Qemu-devel] [PATCH v1 1/1] cadence_gem: Correct Marvell PHY SPCFC reset value

2015-09-03 Thread Edgar E. Iglesias
On Thu, Sep 03, 2015 at 03:10:52PM -0700, Alistair Francis wrote: > Bit 15 of the PHY Specific Status Register is reserved and > should remain 0. Fix the reset value to ensure that the 15th > bit is not set. > > Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias > --- > http://www

[Qemu-devel] [PATCH v1 1/1] cadence_gem: Correct Marvell PHY SPCFC reset value

2015-09-03 Thread Alistair Francis
Bit 15 of the PHY Specific Status Register is reserved and should remain 0. Fix the reset value to ensure that the 15th bit is not set. Signed-off-by: Alistair Francis --- http://www.marvell.com/transceivers/assets/Marvell-88E3016-Fast-Ethernet.pdf hw/net/cadence_gem.c |2 +- 1 files change