Re: [Qemu-devel] [PATCH v1 00/21] RISC-V QEMU Port Submission v1

2018-01-08 Thread Andrea Bolognani
On Wed, 2018-01-03 at 22:06 +, Richard W.M. Jones wrote: > On Thu, Jan 04, 2018 at 10:50:06AM +1300, Michael Clark wrote: > > > (2) I'm worried that this patch starts off using virtio-mmio instead > > > of virtio-pci. virtio-pci is better in every respect than > > > virtio-mmio, and while it m

Re: [Qemu-devel] [PATCH v1 00/21] RISC-V QEMU Port Submission v1

2018-01-08 Thread Christoph Hellwig
> The RISC-V QEMU port implements the following specifications: > - RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2 > - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1 > - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10 What is the reas

Re: [Qemu-devel] [PATCH v1 00/21] RISC-V QEMU Port Submission v1

2018-01-05 Thread Paolo Bonzini
On 05/01/2018 13:25, Fam Zheng wrote: >> >> CheckpatchFlags: --ignore-long-lines > It sounds feasible. Putting these flags after a --- line will keep commit > message clean. > > OTOH I think we should spend effort on patching checkpatch.pl to implement > this. Maybe just add something like Pa

Re: [Qemu-devel] [PATCH v1 00/21] RISC-V QEMU Port Submission v1

2018-01-05 Thread Alex Bennée
Fam Zheng writes: > On Fri, 01/05 11:49, Alex Bennée wrote: >> >> Fam Zheng writes: >> >> > On Wed, 01/03 15:54, Michael Clark wrote: >> >> On Wed, Jan 3, 2018 at 3:41 PM, Fam Zheng wrote: >> >> >> >> > On Wed, 01/03 15:00, Michael Clark wrote: >> >> > > So it's essentially one error, the sing

Re: [Qemu-devel] [PATCH v1 00/21] RISC-V QEMU Port Submission v1

2018-01-05 Thread Fam Zheng
On Fri, 01/05 11:49, Alex Bennée wrote: > > Fam Zheng writes: > > > On Wed, 01/03 15:54, Michael Clark wrote: > >> On Wed, Jan 3, 2018 at 3:41 PM, Fam Zheng wrote: > >> > >> > On Wed, 01/03 15:00, Michael Clark wrote: > >> > > So it's essentially one error, the single line case pattern for > >>

Re: [Qemu-devel] [PATCH v1 00/21] RISC-V QEMU Port Submission v1

2018-01-05 Thread Alex Bennée
Fam Zheng writes: > On Wed, 01/03 15:54, Michael Clark wrote: >> On Wed, Jan 3, 2018 at 3:41 PM, Fam Zheng wrote: >> >> > On Wed, 01/03 15:00, Michael Clark wrote: >> > > So it's essentially one error, the single line case pattern for >> > > table-driven decode which flags for long lines and as

Re: [Qemu-devel] [PATCH v1 00/21] RISC-V QEMU Port Submission v1

2018-01-03 Thread Richard W.M. Jones
On Thu, Jan 04, 2018 at 10:50:06AM +1300, Michael Clark wrote: > On Thu, Jan 4, 2018 at 12:35 AM, Richard W.M. Jones > wrote: > > > Just a few small points: > > > > (1) I've built Fedora RPMs from this patch set [approximately - I'm > > using a very slightly different / slightly older version, bu

Re: [Qemu-devel] [PATCH v1 00/21] RISC-V QEMU Port Submission v1

2018-01-03 Thread Michael Clark
On Thu, Jan 4, 2018 at 12:35 AM, Richard W.M. Jones wrote: > Just a few small points: > > (1) I've built Fedora RPMs from this patch set [approximately - I'm > using a very slightly different / slightly older version, but it's not > substantively different]: > > http://copr-fe.cloud.fedoraproje

Re: [Qemu-devel] [PATCH v1 00/21] RISC-V QEMU Port Submission v1

2018-01-03 Thread Richard W.M. Jones
Just a few small points: (1) I've built Fedora RPMs from this patch set [approximately - I'm using a very slightly different / slightly older version, but it's not substantively different]: http://copr-fe.cloud.fedoraproject.org/coprs/rjones/riscv/ It works well for me building plenty of Fedor

Re: [Qemu-devel] [PATCH v1 00/21] RISC-V QEMU Port Submission v1

2018-01-02 Thread Fam Zheng
On Wed, 01/03 15:54, Michael Clark wrote: > On Wed, Jan 3, 2018 at 3:41 PM, Fam Zheng wrote: > > > On Wed, 01/03 15:00, Michael Clark wrote: > > > So it's essentially one error, the single line case pattern for > > > table-driven decode which flags for long lines and asks to separate break > > >

Re: [Qemu-devel] [PATCH v1 00/21] RISC-V QEMU Port Submission v1

2018-01-02 Thread Michael Clark
On Wed, Jan 3, 2018 at 3:41 PM, Fam Zheng wrote: > On Wed, 01/03 15:00, Michael Clark wrote: > > So it's essentially one error, the single line case pattern for > > table-driven decode which flags for long lines and asks to separate break > > onto its own line. > > > > We have actually reduced th

Re: [Qemu-devel] [PATCH v1 00/21] RISC-V QEMU Port Submission v1

2018-01-02 Thread Fam Zheng
On Wed, 01/03 15:00, Michael Clark wrote: > So it's essentially one error, the single line case pattern for > table-driven decode which flags for long lines and asks to separate break > onto its own line. > > We have actually reduced the readability of other parts of the code to > conform to this

Re: [Qemu-devel] [PATCH v1 00/21] RISC-V QEMU Port Submission v1

2018-01-02 Thread Michael Clark
put below for >> more information: >> >> Type: series >> Message-id: 1514940265-18093-1-git-send-email-...@sifive.com >> Subject: [Qemu-devel] [PATCH v1 00/21] RISC-V QEMU Port Submission v1 >> >> === TEST SCRIPT BEGIN === >> #!/bin/bash >> >

Re: [Qemu-devel] [PATCH v1 00/21] RISC-V QEMU Port Submission v1

2018-01-02 Thread Michael Clark
his series seems to have some coding style problems. See output below for > more information: > > Type: series > Message-id: 1514940265-18093-1-git-send-email-...@sifive.com > Subject: [Qemu-devel] [PATCH v1 00/21] RISC-V QEMU Port Submission v1 > > === TEST SCRIPT BEGIN === &

Re: [Qemu-devel] [PATCH v1 00/21] RISC-V QEMU Port Submission v1

2018-01-02 Thread no-reply
Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 1514940265-18093-1-git-send-email-...@sifive.com Subject: [Qemu-devel] [PATCH v1 00/21] RISC-V QEMU Port Submission v1 === TEST SCRIPT BEGIN === #!/bin/bash BASE=base n=1

[Qemu-devel] [PATCH v1 00/21] RISC-V QEMU Port Submission v1

2018-01-02 Thread Michael Clark
QEMU RISC-V Emulation Support (RV64GC, RV32GC) *** Background *** "RISC-V is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on archit