Re: [Qemu-devel] [PATCH v1] s390x/cpumodel: allow to enable "idtes" feature for TCG

2017-07-03 Thread Richard Henderson
On 07/03/2017 04:07 AM, Thomas Huth wrote: On 30.06.2017 21:22, Richard Henderson wrote: On 06/29/2017 12:05 AM, Thomas Huth wrote: However, I'm not sure whether you can simply ignore the clearing-by-ASCE stuff in this case. For example, according to the PoP: "When the clearing-by-ASCE-option

Re: [Qemu-devel] [PATCH v1] s390x/cpumodel: allow to enable "idtes" feature for TCG

2017-07-03 Thread David Hildenbrand
On 03.07.2017 13:07, Thomas Huth wrote: > On 30.06.2017 21:22, Richard Henderson wrote: >> On 06/29/2017 12:05 AM, Thomas Huth wrote: >>> However, I'm not sure whether you can simply ignore the clearing-by-ASCE >>> stuff in this case. For example, according to the PoP: >>> >>> "When the clearing-by

Re: [Qemu-devel] [PATCH v1] s390x/cpumodel: allow to enable "idtes" feature for TCG

2017-07-03 Thread Thomas Huth
On 30.06.2017 21:22, Richard Henderson wrote: > On 06/29/2017 12:05 AM, Thomas Huth wrote: >> However, I'm not sure whether you can simply ignore the clearing-by-ASCE >> stuff in this case. For example, according to the PoP: >> >> "When the clearing-by-ASCE-option bit (bit 52 of gen- >> eral regi

Re: [Qemu-devel] [PATCH v1] s390x/cpumodel: allow to enable "idtes" feature for TCG

2017-06-30 Thread Richard Henderson
On 06/29/2017 12:05 AM, Thomas Huth wrote: However, I'm not sure whether you can simply ignore the clearing-by-ASCE stuff in this case. For example, according to the PoP: "When the clearing-by-ASCE-option bit (bit 52 of gen- eral register R2 is one), the M4 field is ignored." And the idte hel

Re: [Qemu-devel] [PATCH v1] s390x/cpumodel: allow to enable "idtes" feature for TCG

2017-06-29 Thread Thomas Huth
On 28.06.2017 19:02, David Hildenbrand wrote: > On 28.06.2017 16:21, Thomas Huth wrote: >> On 27.06.2017 18:10, David Hildenbrand wrote: >>> STFL bit 4 and 5 are just indications to the guest, which TLB entries an >>> IDTE call will clear. These are performance indicators for the guest. >>> >>> STF

Re: [Qemu-devel] [PATCH v1] s390x/cpumodel: allow to enable "idtes" feature for TCG

2017-06-28 Thread David Hildenbrand
On 28.06.2017 16:21, Thomas Huth wrote: > On 27.06.2017 18:10, David Hildenbrand wrote: >> STFL bit 4 and 5 are just indications to the guest, which TLB entries an >> IDTE call will clear. These are performance indicators for the guest. >> >> STFL bit 4: >> INVALIDATE DAT TABLE ENTRY (IDTE) per

Re: [Qemu-devel] [PATCH v1] s390x/cpumodel: allow to enable "idtes" feature for TCG

2017-06-28 Thread Thomas Huth
On 27.06.2017 18:10, David Hildenbrand wrote: > STFL bit 4 and 5 are just indications to the guest, which TLB entries an > IDTE call will clear. These are performance indicators for the guest. > > STFL bit 4: > INVALIDATE DAT TABLE ENTRY (IDTE) performs > the invalidation-and-clearing oper

[Qemu-devel] [PATCH v1] s390x/cpumodel: allow to enable "idtes" feature for TCG

2017-06-27 Thread David Hildenbrand
STFL bit 4 and 5 are just indications to the guest, which TLB entries an IDTE call will clear. These are performance indicators for the guest. STFL bit 4: INVALIDATE DAT TABLE ENTRY (IDTE) performs the invalidation-and-clearing operation by selectively clearing TLB segment-table entrie