On Tue, Mar 3, 2015 at 9:05 AM, Peter Crosthwaite
wrote:
> On Mon, Mar 2, 2015 at 2:53 PM, Alistair Francis
> wrote:
>> On Tue, Mar 3, 2015 at 6:06 AM, Peter Crosthwaite
>> wrote:
>>> On Thu, Feb 26, 2015 at 7:38 PM, Alistair Francis
>>> wrote:
On Tue, Feb 24, 2015 at 9:04 AM, Peter Crosth
On Mon, Mar 2, 2015 at 2:53 PM, Alistair Francis
wrote:
> On Tue, Mar 3, 2015 at 6:06 AM, Peter Crosthwaite
> wrote:
>> On Thu, Feb 26, 2015 at 7:38 PM, Alistair Francis
>> wrote:
>>> On Tue, Feb 24, 2015 at 9:04 AM, Peter Crosthwaite
>>> wrote:
Hi Peter and all,
Xilinx's next ge
On Tue, Mar 3, 2015 at 6:06 AM, Peter Crosthwaite
wrote:
> On Thu, Feb 26, 2015 at 7:38 PM, Alistair Francis
> wrote:
>> On Tue, Feb 24, 2015 at 9:04 AM, Peter Crosthwaite
>> wrote:
>>> Hi Peter and all,
>>>
>>> Xilinx's next gen SoC has been announced. This series adds a SoC and
>>> machine mod
On Thu, Feb 26, 2015 at 7:38 PM, Alistair Francis
wrote:
> On Tue, Feb 24, 2015 at 9:04 AM, Peter Crosthwaite
> wrote:
>> Hi Peter and all,
>>
>> Xilinx's next gen SoC has been announced. This series adds a SoC and
>> machine model.
>>
>> Series start with addition of ARM cortex A53 support (P1 a
On Tue, Feb 24, 2015 at 9:04 AM, Peter Crosthwaite
wrote:
> Hi Peter and all,
>
> Xilinx's next gen SoC has been announced. This series adds a SoC and
> machine model.
>
> Series start with addition of ARM cortex A53 support (P1 and P2). The
> Soc skeleton is then added with GIC, EMACs and UARTs a
Hi Peter and all,
Xilinx's next gen SoC has been announced. This series adds a SoC and
machine model.
Series start with addition of ARM cortex A53 support (P1 and P2). The
Soc skeleton is then added with GIC, EMACs and UARTs are added. The
pre-existing models for GEM and UART are not SoC friendly
