Re: [Qemu-devel] [PATCH for-4.1] target/arm: Limit ID register assertions to TCG

2019-07-19 Thread Philippe Mathieu-Daudé
On 7/18/19 2:59 PM, Peter Maydell wrote: > In arm_cpu_realizefn() we make several assertions about the values of > guest ID registers: > * if the CPU provides AArch32 v7VE or better it must advertise the >ARM_DIV feature > * if the CPU provides AArch32 A-profile v6 or better it must >adve

Re: [Qemu-devel] [PATCH for-4.1] target/arm: Limit ID register assertions to TCG

2019-07-18 Thread Laszlo Ersek
On 07/18/19 14:59, Peter Maydell wrote: > In arm_cpu_realizefn() we make several assertions about the values of > guest ID registers: > * if the CPU provides AArch32 v7VE or better it must advertise the >ARM_DIV feature > * if the CPU provides AArch32 A-profile v6 or better it must >adver

Re: [Qemu-devel] [PATCH for-4.1] target/arm: Limit ID register assertions to TCG

2019-07-18 Thread Richard Henderson
On 7/18/19 5:59 AM, Peter Maydell wrote: > In arm_cpu_realizefn() we make several assertions about the values of > guest ID registers: > * if the CPU provides AArch32 v7VE or better it must advertise the >ARM_DIV feature > * if the CPU provides AArch32 A-profile v6 or better it must >adve

[Qemu-devel] [PATCH for-4.1] target/arm: Limit ID register assertions to TCG

2019-07-18 Thread Peter Maydell
In arm_cpu_realizefn() we make several assertions about the values of guest ID registers: * if the CPU provides AArch32 v7VE or better it must advertise the ARM_DIV feature * if the CPU provides AArch32 A-profile v6 or better it must advertise the Jazelle feature These are essentially cons