On 01/31/2011 12:33 AM, Aurelien Jarno wrote:
> This week-end I have tested it emulating an x86-64 machine on x86-64,
> with all the patch series applied. I have measured the boot time from
> the bootloader up to the graphical environment of a Debian installation
> I used -snapshot to make sure the
Hi,
On Tue, Jan 25, 2011 at 01:27:49PM +0100, Edgar E. Iglesias wrote:
> On Mon, Jan 10, 2011 at 07:23:46PM -0800, Richard Henderson wrote:
> > Special case deposits that are implementable with byte and word stores.
> > Otherwise implement with double-word shift plus rotates.
> >
> > Expose tcg_s
Richard Henderson wrote:
> On 01/26/2011 11:09 AM, Alexander Graf wrote:
>
>> Please be aware of the fact that I'm currently reworking the whole CC
>> model, so if you start working on the register acceleration now there
>> will be conflicts for sure :).
>>
>
> Roger.
>
>
>> Do you have
On 01/26/2011 11:09 AM, Alexander Graf wrote:
> Please be aware of the fact that I'm currently reworking the whole CC
> model, so if you start working on the register acceleration now there
> will be conflicts for sure :).
Roger.
> Do you have code to test it with?
Er, I assume I can pull someth
Richard Henderson wrote:
> On 01/26/2011 11:01 AM, Alexander Graf wrote:
>
>>> As far as I know, it does not happen at random. Which seems to be
>>> what you are suggesting.
>>>
>> It happens on load/store and potentially helpers. The main difference
>> IIUC between globals and temps is
On 01/26/2011 11:01 AM, Alexander Graf wrote:
>> As far as I know, it does not happen at random. Which seems to be
>> what you are suggesting.
>
> It happens on load/store and potentially helpers. The main difference
> IIUC between globals and temps is that globals are kept in registers as
> lon
Richard Henderson wrote:
> On 01/26/2011 10:27 AM, Alexander Graf wrote:
>
>> What do I do on a page fault now? I could rerun the translator to find
>> out which registers would be stuck in a temporary, but I have no way to
>> actually read the temporary's value, as all register state is thrown
On 01/26/2011 10:27 AM, Alexander Graf wrote:
> What do I do on a page fault now? I could rerun the translator to find
> out which registers would be stuck in a temporary, but I have no way to
> actually read the temporary's value, as all register state is thrown
> away on a page fault IIUC.
When
Richard Henderson wrote:
> On 01/26/2011 08:50 AM, Alexander Graf wrote:
>
>> Oh, you mean basically to have the following:
>>
>> TCGv_i32 regs32[16];
>> TCGv_i64 regs[16];
>>
>> Then declare both as globals with offset and just switch between the
>> access type using a disas struct variable. On
On 01/26/2011 08:50 AM, Alexander Graf wrote:
> Oh, you mean basically to have the following:
>
> TCGv_i32 regs32[16];
> TCGv_i64 regs[16];
>
> Then declare both as globals with offset and just switch between the
> access type using a disas struct variable. Once the TB ends, I'd
> obviously have
Richard Henderson wrote:
> On 01/26/2011 08:00 AM, Alexander Graf wrote:
>
>> Keeping it only inside of the translator would break on page faults, as
>> the lower 32 bits of the register would lie around in a temporary which
>> is invisible for the page fault resolver.
>>
>
> Given that QEM
On 01/26/2011 08:00 AM, Alexander Graf wrote:
> Keeping it only inside of the translator would break on page faults, as
> the lower 32 bits of the register would lie around in a temporary which
> is invisible for the page fault resolver.
Given that QEMU doesn't support truely async signals, and th
On 01/26/2011 06:00 PM, Alexander Graf wrote:
Richard Henderson wrote:
> On 01/26/2011 01:23 AM, Alexander Graf wrote:
>
>> agraf@toonie:/studio/s390/qemu-s390> grep deposit target-s390x/translate.c
>> tcg_gen_deposit_i64(regs[reg], regs[reg], tmp, 0, 32);
>> tcg_gen_deposit_i64(regs
Richard Henderson wrote:
> On 01/26/2011 01:23 AM, Alexander Graf wrote:
>
>> agraf@toonie:/studio/s390/qemu-s390> grep deposit target-s390x/translate.c
>> tcg_gen_deposit_i64(regs[reg], regs[reg], tmp, 0, 32);
>> tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 32);
>> tcg_gen_depos
On 01/26/2011 01:23 AM, Alexander Graf wrote:
> agraf@toonie:/studio/s390/qemu-s390> grep deposit target-s390x/translate.c
> tcg_gen_deposit_i64(regs[reg], regs[reg], tmp, 0, 32);
> tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 32);
> tcg_gen_deposit_i64(regs[reg], regs[reg], tmp, 0,
On 26.01.2011, at 09:53, Edgar E. Iglesias wrote:
> On Tue, Jan 25, 2011 at 02:07:15PM -0800, Richard Henderson wrote:
>> On 01/25/2011 08:48 AM, Edgar E. Iglesias wrote:
>>> OK, I see. Maybe we should try to emit an insn sequence more similar
>>> to what tcg was emitting (for the non 8 & 16-bit
On Tue, Jan 25, 2011 at 02:07:15PM -0800, Richard Henderson wrote:
> On 01/25/2011 08:48 AM, Edgar E. Iglesias wrote:
> > OK, I see. Maybe we should try to emit an insn sequence more similar
> > to what tcg was emitting (for the non 8 & 16-bit deposits)?
> > That ought too at least give similar res
On 01/25/2011 08:48 AM, Edgar E. Iglesias wrote:
> OK, I see. Maybe we should try to emit an insn sequence more similar
> to what tcg was emitting (for the non 8 & 16-bit deposits)?
> That ought too at least give similar results as before for those and
> give us a speedup for the byte and word move
On Tue, Jan 25, 2011 at 08:13:53AM -0800, Richard Henderson wrote:
> On 01/25/2011 04:27 AM, Edgar E. Iglesias wrote:
> > I've tested this patch a bit and got mixed results. I tested with patched
> > CRIS and MicroBlaze translators. The patch works OK (it doesn't break
> > anything) for the usecase
On 01/25/2011 04:27 AM, Edgar E. Iglesias wrote:
> I've tested this patch a bit and got mixed results. I tested with patched
> CRIS and MicroBlaze translators. The patch works OK (it doesn't break
> anything) for the usecases I had but I saw a bit of a slowdown with
> MicroBlaze (compare to not usi
On Mon, Jan 10, 2011 at 07:23:46PM -0800, Richard Henderson wrote:
> Special case deposits that are implementable with byte and word stores.
> Otherwise implement with double-word shift plus rotates.
>
> Expose tcg_scratch_alloc to the backend for allocation of scratch registers.
>
> Signed-off-b
Special case deposits that are implementable with byte and word stores.
Otherwise implement with double-word shift plus rotates.
Expose tcg_scratch_alloc to the backend for allocation of scratch registers.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c | 67 +++
Special case deposits that are implementable with byte and word stores.
Otherwise implement with double-word shift plus rotates.
Expose tcg_reg_alloc to the backend for allocation of scratch registers.
There's an edge condition that cannot actually happen at the moment due
to a bug elsewhere in th
23 matches
Mail list logo
