On Tue, Jan 29, 2019 at 6:57 PM Jim Wilson wrote:
>
> Adds a debugger field to CPURISCVState. Disable mode checks in riscv_csrrw
> when true.
>
> Signed-off-by: Jim Wilson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.h | 3 +++
> target/riscv/csr.c | 16
Adds a debugger field to CPURISCVState. Disable mode checks in riscv_csrrw
when true.
Signed-off-by: Jim Wilson
---
target/riscv/cpu.h | 3 +++
target/riscv/csr.c | 16
2 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
inde
