Re: [Qemu-devel] [PATCH 3/5 v2] RISC-V: Map gdb CSR reg numbers to hw reg numbers.

2019-01-28 Thread Jim Wilson
On Tue, Jan 22, 2019 at 1:45 PM Alistair Francis wrote: > I think it makes more sense to just define the variable in the > gdbstubs.c file then. Can you move it to patch 5? Yes, that is no problem. That makes patch 3 a lot smaller and patch 5 a lot bigger, but it is the same code as before, just

Re: [Qemu-devel] [PATCH 3/5 v2] RISC-V: Map gdb CSR reg numbers to hw reg numbers.

2019-01-22 Thread Alistair Francis
On Sun, Dec 30, 2018 at 11:22 AM Jim Wilson wrote: > > On Sat, Dec 29, 2018 at 2:23 PM Richard Henderson > wrote: > > On 12/29/18 9:09 AM, Jim Wilson wrote: > > > +int csr_register_map[] = { > > > > static const? > > If I add static const here, then I get a build error if this patch is > applied

Re: [Qemu-devel] [PATCH 3/5 v2] RISC-V: Map gdb CSR reg numbers to hw reg numbers.

2018-12-30 Thread Jim Wilson
On Sat, Dec 29, 2018 at 2:23 PM Richard Henderson wrote: > On 12/29/18 9:09 AM, Jim Wilson wrote: > > +int csr_register_map[] = { > > static const? If I add static const here, then I get a build error if this patch is applied to the tree but the following patch #5 that uses the variable is not ap

Re: [Qemu-devel] [PATCH 3/5 v2] RISC-V: Map gdb CSR reg numbers to hw reg numbers.

2018-12-29 Thread Richard Henderson
On 12/29/18 9:09 AM, Jim Wilson wrote: > +++ b/target/riscv/csr-map.h > @@ -0,0 +1,248 @@ > +/* > + * The GDB CSR xml files list them in documentation order, not numerical > order, > + * and are missing entries for unnamed CSRs. So we need to map the gdb > numbers > + * to the hardware numbers.

[Qemu-devel] [PATCH 3/5 v2] RISC-V: Map gdb CSR reg numbers to hw reg numbers.

2018-12-28 Thread Jim Wilson
The gdb CSR xml file has registers in documentation order, not numerical order, so we need a table to map the register numbers. This also adds some missing CSR_* register macros. Signed-off-by: Jim Wilson --- target/riscv/cpu_bits.h | 35 ++- target/riscv/csr-map.h | 248 +