Re: [Qemu-devel] [PATCH 3/4] target-mips:Support for Cavium specific instructions

2011-08-15 Thread Richard Henderson
> } > +#if defined(TARGET_MIPS64) > +/* set on equal/not equal immidiate */ You need blank lines between all of these functions. Also, "immediate" is misspelled. > +tcg_gen_xori_tl(t0, t0, uimm); > +switch (opc) { > +case OPC_SEQI: > +tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr[

[Qemu-devel] [PATCH 3/4] target-mips:Support for Cavium specific instructions

2011-08-15 Thread khansa
From: Ehsan-ul-Haq, Abdul Qadeer, Abdul Waheed, Khansa Butt Signed-off-by: Khansa Butt --- target-mips/cpu.h |7 + target-mips/helper.h|5 + target-mips/machine.c | 12 ++ target-mips/op_helper.c | 72 target-mips/translate.c | 434