Il 27/05/2014 22:30, Bandan Das ha scritto:
@@ -996,15 +995,14 @@ static inline void cpu_x86_load_seg_cache(CPUX86State
*env,
#endif
{
/* legacy / compatibility case */
-if (!(env->cr[0] & CR0_PE_MASK))
-cpl = 0;
-
Paolo Bonzini writes:
> CS.RPL is not equal to the CPL in the few instructions between
> setting CR0.PE and reloading CS. We get this right in the common
> case, because writes to CR0 do not modify the CPL, but it would
> not be enough if an SMI comes exactly during that brief period.
> Were thi
On Wed, May 21, 2014 at 04:18:22PM +0200, Paolo Bonzini wrote:
> Il 21/05/2014 16:05, Kevin O'Connor ha scritto:
> >On Wed, May 21, 2014 at 01:13:21PM +0200, Paolo Bonzini wrote:
> >>I cannot reproduce this. I can see the breakage with current master, and I
> >>can see your patch fixing it. It ke
Il 21/05/2014 16:05, Kevin O'Connor ha scritto:
On Wed, May 21, 2014 at 01:13:21PM +0200, Paolo Bonzini wrote:
Il 20/05/2014 23:54, Kevin O'Connor ha scritto:
On Fri, May 16, 2014 at 09:59:25PM +0200, Paolo Bonzini wrote:
CS.RPL is not equal to the CPL in the few instructions between
setting C
On Wed, May 21, 2014 at 01:13:21PM +0200, Paolo Bonzini wrote:
> Il 20/05/2014 23:54, Kevin O'Connor ha scritto:
> >On Fri, May 16, 2014 at 09:59:25PM +0200, Paolo Bonzini wrote:
> >>CS.RPL is not equal to the CPL in the few instructions between
> >>setting CR0.PE and reloading CS. We get this rig
Il 20/05/2014 23:54, Kevin O'Connor ha scritto:
On Fri, May 16, 2014 at 09:59:25PM +0200, Paolo Bonzini wrote:
CS.RPL is not equal to the CPL in the few instructions between
setting CR0.PE and reloading CS. We get this right in the common
case, because writes to CR0 do not modify the CPL, but i
On Fri, May 16, 2014 at 09:59:25PM +0200, Paolo Bonzini wrote:
> CS.RPL is not equal to the CPL in the few instructions between
> setting CR0.PE and reloading CS. We get this right in the common
> case, because writes to CR0 do not modify the CPL, but it would
> not be enough if an SMI comes exact
CS.RPL is not equal to the CPL in the few instructions between
setting CR0.PE and reloading CS. We get this right in the common
case, because writes to CR0 do not modify the CPL, but it would
not be enough if an SMI comes exactly during that brief period.
Were this to happen, the RSM instruction w
Il 15/05/2014 20:38, Kevin O'Connor ha scritto:
On Thu, May 15, 2014 at 06:56:56PM +0200, Paolo Bonzini wrote:
CS.RPL is not equal to the CPL in the few instructions between
setting CR0.PE and reloading CS. We get this right in the common
case, because writes to CR0 do not modify the CPL, but i
On Thu, May 15, 2014 at 06:56:56PM +0200, Paolo Bonzini wrote:
> CS.RPL is not equal to the CPL in the few instructions between
> setting CR0.PE and reloading CS. We get this right in the common
> case, because writes to CR0 do not modify the CPL, but it would
> not be enough if an SMI comes exact
CS.RPL is not equal to the CPL in the few instructions between
setting CR0.PE and reloading CS. We get this right in the common
case, because writes to CR0 do not modify the CPL, but it would
not be enough if an SMI comes exactly during that brief period.
Were this to happen, the RSM instruction w
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