On 08/11/2014 09:23 AM, Tom Musta wrote:
> +#if defined(TARGET_PPC64)
> +tcg_gen_andi_tl(t0, t0, MASK(32, 63));
> +#endif
Err. this is just simple zero-extension.
> tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
Why not combine with the mov as
tcg_gen_ext32u_tl
which will jus
The rlwnm specification includes the ROTL32 operation, which is defined
to be a left rotation of two copies of the least significant 32 bits of
the source GPR.
The current implementation is incorrect on 64-bit implementations in that
it rotates a single copy of the least significant 32 bits, paddi
