Re: [Qemu-devel] [PATCH 17/60] AArch64: Add dup GPR->Vec instruction emulation

2013-09-27 Thread Richard Henderson
On 09/26/2013 05:48 PM, Alexander Graf wrote: > +case 0x0e: > +if (!get_bits(insn, 31, 1) && !get_bits(insn, 29, 1) && > +(get_bits(insn, 10, 6) == 0x3)) { > +handle_dupg(s, insn); Is this really better than (insn & y) == x ? r~

[Qemu-devel] [PATCH 17/60] AArch64: Add dup GPR->Vec instruction emulation

2013-09-26 Thread Alexander Graf
This patch adds emulation for the DUP instruction flavor that copies GPR contents into vector register parts. Signed-off-by: Alexander Graf --- target-arm/translate-a64.c | 55 ++ 1 file changed, 55 insertions(+) diff --git a/target-arm/translate-a64.