On 9 October 2017 at 17:18, Andrey Smirnov wrote:
> On Fri, Oct 6, 2017 at 7:38 AM, Peter Maydell
> wrote:
>> On 18 September 2017 at 20:50, Andrey Smirnov
>> wrote:
>>> +static void fsl_imx7_realize(DeviceState *dev, Error **errp)
>>> +{
>>> +FslIMX7State *s = FSL_IMX7(dev);
>>> +Obje
On Fri, Oct 6, 2017 at 7:38 AM, Peter Maydell wrote:
> On 18 September 2017 at 20:50, Andrey Smirnov
> wrote:
>> For now we only support the following devices:
>> * up to 2 Cortex A9 cores (SMP works with PSCI)
>> * A7 MPCORE (identical to A15 MPCORE)
>> * 7 i.MX UARTs
>> * 1 CCM
On 18 September 2017 at 20:50, Andrey Smirnov wrote:
> For now we only support the following devices:
> * up to 2 Cortex A9 cores (SMP works with PSCI)
> * A7 MPCORE (identical to A15 MPCORE)
> * 7 i.MX UARTs
> * 1 CCM device
> * 2 Ethernet controllers (FEC)
> * 3 SD contro
For now we only support the following devices:
* up to 2 Cortex A9 cores (SMP works with PSCI)
* A7 MPCORE (identical to A15 MPCORE)
* 7 i.MX UARTs
* 1 CCM device
* 2 Ethernet controllers (FEC)
* 3 SD controllers (USDHC)
* 1 SNVS device
* 1 WDT device
Cc: Peter Mayd
