On 09/14/2015 07:11 PM, Richard Henderson wrote:
On 09/13/2015 01:34 AM, Bastian Koppelmann wrote:
Looking at the article, user mode seems to be optional, so I'm not against it,
but it does look weird. How does ork1sim do it?
It's haphazard. There are checks for supervisor in the l_mtspr and
On 09/13/2015 01:34 AM, Bastian Koppelmann wrote:
> Looking at the article, user mode seems to be optional, so I'm not against it,
> but it does look weird. How does ork1sim do it?
It's haphazard. There are checks for supervisor in the l_mtspr and l_mfspr
insns, but not other uses of the sprs, su
On 09/06/2015 10:36 PM, Richard Henderson wrote:
On Sep 5, 2015 14:35, Bastian Koppelmann wrote:
IIRC a lot of the registers are supervisor only, e.g. VR, NPC or SR and
the manual is fairly clear about that. User mode cpu ought not to read
these registers unconditionally.
When I last discuss
On Sep 5, 2015 14:35, Bastian Koppelmann wrote:
> IIRC a lot of the registers are supervisor only, e.g. VR, NPC or SR and
> the manual is fairly clear about that. User mode cpu ought not to read
> these registers unconditionally.
When I last discussed this on the openrisc list, back in March,
On 09/03/2015 02:17 AM, Richard Henderson wrote:
-if (dc->mem_idx == MMU_USER_IDX) {
-gen_illegal_exception(dc);
-return;
+{
+TCGv_i32 tmp = tcg_temp_new_i32();
+tcg_gen_trunc_tl_i32(tmp, cpu_R[ra]);
+tcg_gen_ori_i32(tmp,
The architecture manual doesn't say these opcodes are user only.
Leaving them disabled excludes user mode from accessing interesting
SPRs like MACLO/MACHI.
Signed-off-by: Richard Henderson
---
target-openrisc/helper.h | 4 +--
target-openrisc/sys_helper.c | 77 +-
